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Fix SPI communication #43

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1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -2,3 +2,4 @@
/example/target
**/*.rs.bk
Cargo.lock
.idea
12 changes: 8 additions & 4 deletions src/spi.rs
Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,7 @@
use core::future::Future;
#[cfg(feature = "sync")]
use embedded_hal::delay::DelayNs;
use embedded_hal::spi::Operation;
#[cfg(feature = "sync")]
use embedded_hal::spi::SpiDevice;
#[cfg(feature = "async")]
Expand Down Expand Up @@ -157,9 +158,9 @@ where

fn write_register(&mut self, register: u8, payload: u8) -> Result<(), Error<Self::Error>> {
// If the first bit is 0, the register is written.
let transfer = [register & 0x7f, payload];
let data = [register & 0x7f, payload];
self.spi
.transfer(&mut [], &transfer)
.write(&data)
.map_err(|e| Error::Bus(SPIError::SPI(e)))?;
Ok(())
}
Expand Down Expand Up @@ -251,8 +252,11 @@ where
register: u8,
data: &mut [u8],
) -> Result<(), Error<SPIError<SPI::Error>>> {
self.spi
.transfer(data, &[register])
self.spi
.transaction(&mut [
Operation::Write(&[register]),
Operation::Read(data)
])
.await
.map_err(|e| Error::Bus(SPIError::SPI(e)))?;
Ok(())
Expand Down