Skip to content

Commit

Permalink
Replace sizeof(xlen) with xlen
Browse files Browse the repository at this point in the history
  • Loading branch information
@Timmmm
Timmmm committed Sep 26, 2024
1 parent a153600 commit ba5f6d0
Show file tree
Hide file tree
Showing 33 changed files with 399 additions and 399 deletions.
2 changes: 1 addition & 1 deletion model/main.sail
View file
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ $ifdef SYMBOLIC

$include <elf.sail>

function get_entry_point() = to_bits(sizeof(xlen), elf_entry())
function get_entry_point() = to_bits(xlen, elf_entry())

$else

Expand Down
4 changes: 2 additions & 2 deletions model/riscv_fdext_regs.sail
View file
Original file line number Diff line number Diff line change
Expand Up @@ -278,7 +278,7 @@ function rF_or_X_D(i) = {
assert(sys_enable_fdext() != sys_enable_zfinx());
if sys_enable_fdext()
then F_D(i)
else if sizeof(xlen) >= 64
else if xlen >= 64
then X(i)[63..0]
else {
assert(i[0] == bitzero);
Expand Down Expand Up @@ -310,7 +310,7 @@ function wF_or_X_D(i, data) = {
assert(sys_enable_fdext() != sys_enable_zfinx());
if sys_enable_fdext()
then F_D(i) = data
else if sizeof(xlen) >= 64
else if xlen >= 64
then X(i) = sign_extend(data)
else {
assert (i[0] == bitzero);
Expand Down
4 changes: 2 additions & 2 deletions model/riscv_insts_aext.sail
View file
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ function lrsc_width_str(width : word_width) -> string =
function lrsc_width_valid(size : word_width) -> bool = {
match size {
WORD => true,
DOUBLE => sizeof(xlen) >= 64,
DOUBLE => xlen >= 64,
_ => false
}
}
Expand All @@ -48,7 +48,7 @@ function amo_width_valid(size : word_width) -> bool = {
BYTE => extensionEnabled(Ext_Zabha),
HALF => extensionEnabled(Ext_Zabha),
WORD => true,
DOUBLE => sizeof(xlen) >= 64,
DOUBLE => xlen >= 64,
}
}

Expand Down
66 changes: 33 additions & 33 deletions model/riscv_insts_base.sail
View file
Original file line number Diff line number Diff line change
Expand Up @@ -211,21 +211,21 @@ mapping encdec_sop : sop <-> bits(3) = {
RISCV_SRAI <-> 0b101
}

mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SLLI) <-> 0b000000 @ shamt @ rs1 @ 0b001 @ rd @ 0b0010011 if sizeof(xlen) == 64 | shamt[5] == bitzero
mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SRLI) <-> 0b000000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 if sizeof(xlen) == 64 | shamt[5] == bitzero
mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SRAI) <-> 0b010000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 if sizeof(xlen) == 64 | shamt[5] == bitzero
mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SLLI) <-> 0b000000 @ shamt @ rs1 @ 0b001 @ rd @ 0b0010011 if xlen == 64 | shamt[5] == bitzero
mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SRLI) <-> 0b000000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 if xlen == 64 | shamt[5] == bitzero
mapping clause encdec = SHIFTIOP(shamt, rs1, rd, RISCV_SRAI) <-> 0b010000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0010011 if xlen == 64 | shamt[5] == bitzero

function clause execute (SHIFTIOP(shamt, rs1, rd, op)) = {
let rs1_val = X(rs1);
/* the decoder guard should ensure that shamt[5] = 0 for RV32 */
let result : xlenbits = match op {
RISCV_SLLI => if sizeof(xlen) == 32
RISCV_SLLI => if xlen == 32
then rs1_val << shamt[4..0]
else rs1_val << shamt,
RISCV_SRLI => if sizeof(xlen) == 32
RISCV_SRLI => if xlen == 32
then rs1_val >> shamt[4..0]
else rs1_val >> shamt,
RISCV_SRAI => if sizeof(xlen) == 32
RISCV_SRAI => if xlen == 32
then shift_right_arith32(rs1_val, shamt[4..0])
else shift_right_arith64(rs1_val, shamt)
};
Expand Down Expand Up @@ -266,14 +266,14 @@ function clause execute (RTYPE(rs2, rs1, rd, op)) = {
RISCV_AND => rs1_val & rs2_val,
RISCV_OR => rs1_val | rs2_val,
RISCV_XOR => rs1_val ^ rs2_val,
RISCV_SLL => if sizeof(xlen) == 32
RISCV_SLL => if xlen == 32
then rs1_val << (rs2_val[4..0])
else rs1_val << (rs2_val[5..0]),
RISCV_SRL => if sizeof(xlen) == 32
RISCV_SRL => if xlen == 32
then rs1_val >> (rs2_val[4..0])
else rs1_val >> (rs2_val[5..0]),
RISCV_SUB => rs1_val - rs2_val,
RISCV_SRA => if sizeof(xlen) == 32
RISCV_SRA => if xlen == 32
then shift_right_arith32(rs1_val, rs2_val[4..0])
else shift_right_arith64(rs1_val, rs2_val[5..0])
};
Expand Down Expand Up @@ -417,9 +417,9 @@ mapping clause assembly = STORE(imm, rs2, rs1, size, aq, rl)
union clause ast = ADDIW : (bits(12), regidx, regidx)

mapping clause encdec = ADDIW(imm, rs1, rd)
if sizeof(xlen) == 64
if xlen == 64
<-> imm @ rs1 @ 0b000 @ rd @ 0b0011011
if sizeof(xlen) == 64
if xlen == 64

function clause execute (ADDIW(imm, rs1, rd)) = {
let result : xlenbits = sign_extend(imm) + X(rs1);
Expand All @@ -428,33 +428,33 @@ function clause execute (ADDIW(imm, rs1, rd)) = {
}

mapping clause assembly = ADDIW(imm, rs1, rd)
if sizeof(xlen) == 64
if xlen == 64
<-> "addiw" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_signed_12(imm)
if sizeof(xlen) == 64
if xlen == 64

/* ****************************************************************** */
union clause ast = RTYPEW : (regidx, regidx, regidx, ropw)

mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_ADDW)
if sizeof(xlen) == 64
if xlen == 64
<-> 0b0000000 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0111011
if sizeof(xlen) == 64
if xlen == 64
mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_SUBW)
if sizeof(xlen) == 64
if xlen == 64
<-> 0b0100000 @ rs2 @ rs1 @ 0b000 @ rd @ 0b0111011
if sizeof(xlen) == 64
if xlen == 64
mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_SLLW)
if sizeof(xlen) == 64
if xlen == 64
<-> 0b0000000 @ rs2 @ rs1 @ 0b001 @ rd @ 0b0111011
if sizeof(xlen) == 64
if xlen == 64
mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_SRLW)
if sizeof(xlen) == 64
if xlen == 64
<-> 0b0000000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0111011
if sizeof(xlen) == 64
if xlen == 64
mapping clause encdec = RTYPEW(rs2, rs1, rd, RISCV_SRAW)
if sizeof(xlen) == 64
if xlen == 64
<-> 0b0100000 @ rs2 @ rs1 @ 0b101 @ rd @ 0b0111011
if sizeof(xlen) == 64
if xlen == 64

function clause execute (RTYPEW(rs2, rs1, rd, op)) = {
let rs1_val = (X(rs1))[31..0];
Expand All @@ -479,25 +479,25 @@ mapping rtypew_mnemonic : ropw <-> string = {
}

mapping clause assembly = RTYPEW(rs2, rs1, rd, op)
if sizeof(xlen) == 64
if xlen == 64
<-> rtypew_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ reg_name(rs2)
if sizeof(xlen) == 64
if xlen == 64

/* ****************************************************************** */
union clause ast = SHIFTIWOP : (bits(5), regidx, regidx, sopw)

mapping clause encdec = SHIFTIWOP(shamt, rs1, rd, RISCV_SLLIW)
if sizeof(xlen) == 64
if xlen == 64
<-> 0b0000000 @ shamt @ rs1 @ 0b001 @ rd @ 0b0011011
if sizeof(xlen) == 64
if xlen == 64
mapping clause encdec = SHIFTIWOP(shamt, rs1, rd, RISCV_SRLIW)
if sizeof(xlen) == 64
if xlen == 64
<-> 0b0000000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011
if sizeof(xlen) == 64
if xlen == 64
mapping clause encdec = SHIFTIWOP(shamt, rs1, rd, RISCV_SRAIW)
if sizeof(xlen) == 64
if xlen == 64
<-> 0b0100000 @ shamt @ rs1 @ 0b101 @ rd @ 0b0011011
if sizeof(xlen) == 64
if xlen == 64

function clause execute (SHIFTIWOP(shamt, rs1, rd, op)) = {
let rs1_val = (X(rs1))[31..0];
Expand All @@ -517,9 +517,9 @@ mapping shiftiwop_mnemonic : sopw <-> string = {
}

mapping clause assembly = SHIFTIWOP(shamt, rs1, rd, op)
if sizeof(xlen) == 64
if xlen == 64
<-> shiftiwop_mnemonic(op) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_5(shamt)
if sizeof(xlen) == 64
if xlen == 64

/* ****************************************************************** */
union clause ast = FENCE : (bits(4), bits(4))
Expand Down
38 changes: 19 additions & 19 deletions model/riscv_insts_dext.sail
View file
Original file line number Diff line number Diff line change
Expand Up @@ -233,7 +233,7 @@ function haveDoubleFPU() -> bool = extensionEnabled(Ext_D) | extensionEnabled(Ex
/* not used for RV32Zdinx (i.e. RV64-only or D-only). */
val validDoubleRegs : forall 'n, 'n > 0. (implicit('n), vector('n, regidx)) -> bool
function validDoubleRegs(n, regs) = {
if extensionEnabled(Ext_Zdinx) & sizeof(xlen) == 32 then
if extensionEnabled(Ext_Zdinx) & xlen == 32 then
foreach (i from 0 to (n - 1))
if (regs[i][0] == bitone) then return false;
true
Expand Down Expand Up @@ -417,20 +417,20 @@ mapping clause encdec =
/* D instructions, RV64 only */

mapping clause encdec =
F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_L_D) if haveDoubleFPU() & sizeof(xlen) >= 64
<-> 0b110_0001 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & sizeof(xlen) >= 64
F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_L_D) if haveDoubleFPU() & xlen >= 64
<-> 0b110_0001 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & xlen >= 64

mapping clause encdec =
F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_LU_D) if haveDoubleFPU() & sizeof(xlen) >= 64
<-> 0b110_0001 @ 0b00011 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & sizeof(xlen) >= 64
F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_LU_D) if haveDoubleFPU() & xlen >= 64
<-> 0b110_0001 @ 0b00011 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & xlen >= 64

mapping clause encdec =
F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_L) if haveDoubleFPU() & sizeof(xlen) >= 64
<-> 0b110_1001 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & sizeof(xlen) >= 64
F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_L) if haveDoubleFPU() & xlen >= 64
<-> 0b110_1001 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & xlen >= 64

mapping clause encdec =
F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_LU) if haveDoubleFPU() & sizeof(xlen) >= 64
<-> 0b110_1001 @ 0b00011 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & sizeof(xlen) >= 64
F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_LU) if haveDoubleFPU() & xlen >= 64
<-> 0b110_1001 @ 0b00011 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveDoubleFPU() & xlen >= 64

/* Execution semantics ================================ */

Expand Down Expand Up @@ -540,7 +540,7 @@ function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_S)) = {
}

function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_L_D)) = {
assert(sizeof(xlen) >= 64);
assert(xlen >= 64);
let rs1_val_D = F_or_X_D(rs1);
match (select_instr_or_fcsr_rm (rm)) {
None() => { handle_illegal(); RETIRE_FAIL },
Expand All @@ -556,7 +556,7 @@ function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_L_D)) = {
}

function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_LU_D)) = {
assert(sizeof(xlen) >= 64);
assert(xlen >= 64);
let rs1_val_D = F_or_X_D(rs1);
match (select_instr_or_fcsr_rm (rm)) {
None() => { handle_illegal(); RETIRE_FAIL },
Expand All @@ -572,7 +572,7 @@ function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_LU_D)) = {
}

function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_L)) = {
assert(sizeof(xlen) >= 64);
assert(xlen >= 64);
let rs1_val_L = X(rs1)[63..0];
match (select_instr_or_fcsr_rm (rm)) {
None() => { handle_illegal(); RETIRE_FAIL },
Expand All @@ -588,7 +588,7 @@ function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_L)) = {
}

function clause execute (F_UN_RM_TYPE_D(rs1, rm, rd, FCVT_D_LU)) = {
assert(sizeof(xlen) >= 64);
assert(xlen >= 64);
let rs1_val_LU = X(rs1)[63..0];
match (select_instr_or_fcsr_rm (rm)) {
None() => { handle_illegal(); RETIRE_FAIL },
Expand Down Expand Up @@ -905,11 +905,11 @@ mapping clause encdec = F_UN_TYPE_D(rs1, rd, FCLASS_D) if

/* D instructions, RV64 only */

mapping clause encdec = F_UN_TYPE_D(rs1, rd, FMV_X_D) if extensionEnabled(Ext_D) & sizeof(xlen) >= 64
<-> 0b111_0001 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if extensionEnabled(Ext_D) & sizeof(xlen) >= 64
mapping clause encdec = F_UN_TYPE_D(rs1, rd, FMV_X_D) if extensionEnabled(Ext_D) & xlen >= 64
<-> 0b111_0001 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if extensionEnabled(Ext_D) & xlen >= 64

mapping clause encdec = F_UN_TYPE_D(rs1, rd, FMV_D_X) if extensionEnabled(Ext_D) & sizeof(xlen) >= 64
<-> 0b111_1001 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if extensionEnabled(Ext_D) & sizeof(xlen) >= 64
mapping clause encdec = F_UN_TYPE_D(rs1, rd, FMV_D_X) if extensionEnabled(Ext_D) & xlen >= 64
<-> 0b111_1001 @ 0b00000 @ rs1 @ 0b000 @ rd @ 0b101_0011 if extensionEnabled(Ext_D) & xlen >= 64

/* Execution semantics ================================ */

Expand All @@ -934,15 +934,15 @@ function clause execute (F_UN_TYPE_D(rs1, rd, FCLASS_D)) = {
}

function clause execute (F_UN_TYPE_D(rs1, rd, FMV_X_D)) = {
assert(sizeof(xlen) >= 64);
assert(xlen >= 64);
let rs1_val_D = F(rs1)[63..0];
let rd_val_X : xlenbits = sign_extend(rs1_val_D);
X(rd) = rd_val_X;
RETIRE_SUCCESS
}

function clause execute (F_UN_TYPE_D(rs1, rd, FMV_D_X)) = {
assert(sizeof(xlen) >= 64);
assert(xlen >= 64);
let rs1_val_X = X(rs1);
let rd_val_D = rs1_val_X [63..0];
F(rd) = rd_val_D;
Expand Down
24 changes: 12 additions & 12 deletions model/riscv_insts_fext.sail
View file
Original file line number Diff line number Diff line change
Expand Up @@ -586,20 +586,20 @@ mapping clause encdec =
/* F instructions, RV64 only */

mapping clause encdec =
F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_L_S) if haveSingleFPU() & sizeof(xlen) >= 64
<-> 0b110_0000 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU() & sizeof(xlen) >= 64
F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_L_S) if haveSingleFPU() & xlen >= 64
<-> 0b110_0000 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU() & xlen >= 64

mapping clause encdec =
F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_LU_S) if haveSingleFPU() & sizeof(xlen) >= 64
<-> 0b110_0000 @ 0b00011 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU() & sizeof(xlen) >= 64
F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_LU_S) if haveSingleFPU() & xlen >= 64
<-> 0b110_0000 @ 0b00011 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU() & xlen >= 64

mapping clause encdec =
F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_L) if haveSingleFPU() & sizeof(xlen) >= 64
<-> 0b110_1000 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU() & sizeof(xlen) >= 64
F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_L) if haveSingleFPU() & xlen >= 64
<-> 0b110_1000 @ 0b00010 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU() & xlen >= 64

mapping clause encdec =
F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_LU) if haveSingleFPU() & sizeof(xlen) >= 64
<-> 0b110_1000 @ 0b00011 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU() & sizeof(xlen) >= 64
F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_LU) if haveSingleFPU() & xlen >= 64
<-> 0b110_1000 @ 0b00011 @ rs1 @ encdec_rounding_mode (rm) @ rd @ 0b101_0011 if haveSingleFPU() & xlen >= 64

/* Execution semantics ================================ */

Expand Down Expand Up @@ -679,7 +679,7 @@ function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_WU)) = {
}

function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_L_S)) = {
assert(sizeof(xlen) >= 64);
assert(xlen >= 64);
let rs1_val_S = F_or_X_S(rs1);
match (select_instr_or_fcsr_rm (rm)) {
None() => { handle_illegal(); RETIRE_FAIL },
Expand All @@ -695,7 +695,7 @@ function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_L_S)) = {
}

function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_LU_S)) = {
assert(sizeof(xlen) >= 64);
assert(xlen >= 64);
let rs1_val_S = F_or_X_S(rs1);
match (select_instr_or_fcsr_rm (rm)) {
None() => { handle_illegal(); RETIRE_FAIL },
Expand All @@ -711,7 +711,7 @@ function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_LU_S)) = {
}

function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_L)) = {
assert(sizeof(xlen) >= 64);
assert(xlen >= 64);
let rs1_val_L = X(rs1)[63..0];
match (select_instr_or_fcsr_rm (rm)) {
None() => { handle_illegal(); RETIRE_FAIL },
Expand All @@ -727,7 +727,7 @@ function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_L)) = {
}

function clause execute (F_UN_RM_TYPE_S(rs1, rm, rd, FCVT_S_LU)) = {
assert(sizeof(xlen) >= 64);
assert(xlen >= 64);
let rs1_val_LU = X(rs1)[63..0];
match (select_instr_or_fcsr_rm (rm)) {
None() => { handle_illegal(); RETIRE_FAIL },
Expand Down
4 changes: 2 additions & 2 deletions model/riscv_insts_hints.sail
View file
Original file line number Diff line number Diff line change
Expand Up @@ -97,9 +97,9 @@ mapping clause assembly = C_ADD_HINT(rs2)
union clause ast = C_SLLI_HINT : (bits(6), regidx)

mapping clause encdec_compressed = C_SLLI_HINT(nzui5 @ nzui40, rsd)
if (nzui5 @ nzui40 == 0b000000 | rsd == zreg) & (sizeof(xlen) == 64 | nzui5 == 0b0)
if (nzui5 @ nzui40 == 0b000000 | rsd == zreg) & (xlen == 64 | nzui5 == 0b0)
<-> 0b000 @ nzui5 : bits(1) @ rsd : regidx @ nzui40 : bits(5) @ 0b10
if (nzui5 @ nzui40 == 0b000000 | rsd == zreg) & (sizeof(xlen) == 64 | nzui5 == 0b0)
if (nzui5 @ nzui40 == 0b000000 | rsd == zreg) & (xlen == 64 | nzui5 == 0b0)

function clause execute (C_SLLI_HINT(shamt, rsd)) = RETIRE_SUCCESS

Expand Down
Loading

0 comments on commit ba5f6d0

Please sign in to comment.