Merge pull request riscv#514 from lz-bro/timer_configurable

Make CLINT address configurable

debug/gdbserver.py

@@ -912,7 +912,7 @@ def early_applicable(self):
     def test(self):
         self.gdb.b("main:start")
         self.gdb.c()
-        mtime_addr = 0x02000000 + 0xbff8
+        mtime_addr = self.target.clint_addr + 0xbff8
         count = 1024
         output = self.gdb.command(
             f"monitor riscv repeat_read {count} 0x{mtime_addr:x} 4")
@@ -1048,8 +1048,8 @@ def test(self):
 
     def postMortem(self):
         GdbSingleHartTest.postMortem(self)
-        self.gdb.p("*((long long*) 0x200bff8)")
-        self.gdb.p("*((long long*) 0x2004000)")
+        self.gdb.p(f"*((long long*) 0x{self.target.clint_addr + 0xbff8:x})")
+        self.gdb.p(f"*((long long*) 0x{self.target.clint_addr + 0x4000:x})")
         self.gdb.p("interrupt_count")
         self.gdb.p("local")
 

debug/programs/init.h

@@ -1,8 +1,10 @@
 #ifndef INIT_H
 #define INIT_H
 
-#define MTIME           (*(volatile long long *)(0x02000000 + 0xbff8))
-#define MTIMECMP        ((volatile long long *)(0x02000000 + 0x4000))
+#ifdef CLINT
+#define MTIME           (*(volatile long long *)(CLINT + 0xbff8))
+#define MTIMECMP        ((volatile long long *)(CLINT + 0x4000))
+#endif
 
 typedef void* (*trap_handler_t)(unsigned hartid, unsigned mcause, void *mepc,
         void *sp);

debug/programs/run_halt_timing.S

@@ -6,12 +6,16 @@
 # define LREG lw
 # define SREG sw
 # define REGBYTES 4
+#endif
+
+#ifdef CLINT
+#define MTIME_ADDR      CLINT + 0xbff8
 #endif
 
         .global main
 main:
         li      s0, 0
-        li      s1, 0x0200bff8
+        li      s1, MTIME_ADDR
 loop:
         addi    s0, s0, 1
         LREG    s2, 0(s1)

debug/targets.py

@@ -93,9 +93,12 @@ class Target:
     # before starting the test.
     gdb_setup = []
 
-    # Supports mtime at 0x2004000
+    # Supports mtime default at clint_addr + 0x4000
     supports_clint_mtime = True
 
+    # CLINT register address, set to the default value of spike.
+    clint_addr = 0x02000000
+
     # Implements custom debug registers like spike does. It seems unlikely any
     # hardware will every do that.
     implements_custom_test = False
@@ -189,6 +192,7 @@ def do_compile(self, hart, *sources):
             Target.temporary_files.append(self.temporary_binary)
 
         args = list(sources) + [
+                f"-DCLINT={self.clint_addr}",
                 "programs/entry.S", "programs/init.c",
                 f"-DNHARTS={len(self.harts)}",
                 "-I", "../env",