Skip to content

Commit

Permalink
Move extension scattered enum to single file
Browse files Browse the repository at this point in the history
Having this distributed through the code can lead to slightly awkward dependency order issues. We need to keep it scattered though so e.g. CHERI can add its extensions.
  • Loading branch information
Timmmm committed Dec 16, 2024
1 parent 5f4a8e6 commit 859a49c
Show file tree
Hide file tree
Showing 30 changed files with 66 additions and 53 deletions.
4 changes: 2 additions & 2 deletions Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -106,10 +106,10 @@ SAIL_REGS_SRCS += riscv_ext_regs.sail $(SAIL_CHECK_SRCS)
SAIL_REGS_SRCS += riscv_vreg_type.sail riscv_vext_regs.sail

SAIL_ARCH_SRCS = $(PRELUDE)
SAIL_ARCH_SRCS += riscv_types_common.sail riscv_types_ext.sail riscv_types.sail
SAIL_ARCH_SRCS += riscv_extensions.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail
SAIL_ARCH_SRCS += riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail
SAIL_ARCH_SRCS += riscv_mem.sail $(SAIL_VM_SRCS)
SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) riscv_types_kext.sail
SAIL_ARCH_RVFI_SRCS = $(PRELUDE) rvfi_dii.sail riscv_extensions.sail riscv_types_common.sail riscv_types_ext.sail riscv_types.sail riscv_vmem_types.sail $(SAIL_REGS_SRCS) $(SAIL_SYS_SRCS) riscv_platform.sail riscv_mem.sail $(SAIL_VM_SRCS) riscv_types_kext.sail
SAIL_ARCH_SRCS += riscv_types_kext.sail # Shared/common code for the cryptography extension.

SAIL_STEP_SRCS = riscv_step_common.sail riscv_step_ext.sail riscv_decode_ext.sail riscv_fetch.sail riscv_step.sail
Expand Down
61 changes: 61 additions & 0 deletions model/riscv_extensions.sail
Original file line number Diff line number Diff line change
@@ -0,0 +1,61 @@
/*=======================================================================================*/
/* This Sail RISC-V architecture model, comprising all files and */
/* directories except where otherwise noted is subject the BSD */
/* two-clause license in the LICENSE file. */
/* */
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

scattered enum extension

// Bit manipulation
enum clause extension = Ext_B
// Compressed
enum clause extension = Ext_C
// Double precision float
enum clause extension = Ext_D
// Single precision float
enum clause extension = Ext_F
// Multiply/Divide; not Machine!
enum clause extension = Ext_M
// Supervisor
enum clause extension = Ext_S
// Supervisor time compare
enum clause extension = Ext_Sstc
enum clause extension = Ext_Svinval
// User
enum clause extension = Ext_U
// Vector
enum clause extension = Ext_V
enum clause extension = Ext_Zaamo
enum clause extension = Ext_Zabha
enum clause extension = Ext_Zalrsc
enum clause extension = Ext_Zba
enum clause extension = Ext_Zbb
enum clause extension = Ext_Zbc
enum clause extension = Ext_Zbkb
enum clause extension = Ext_Zbkc
enum clause extension = Ext_Zbkx
enum clause extension = Ext_Zbs
enum clause extension = Ext_Zca
enum clause extension = Ext_Zcb
enum clause extension = Ext_Zcd
enum clause extension = Ext_Zcf
enum clause extension = Ext_Zdinx
enum clause extension = Ext_Zfa
enum clause extension = Ext_Zfh
enum clause extension = Ext_Zfhmin
enum clause extension = Ext_Zfinx
enum clause extension = Ext_Zhinx
enum clause extension = Ext_Zicbom
enum clause extension = Ext_Zicboz
enum clause extension = Ext_Zicond
enum clause extension = Ext_Zifencei
enum clause extension = Ext_Zihpm
enum clause extension = Ext_Zknd
enum clause extension = Ext_Zkne
enum clause extension = Ext_Zknh
enum clause extension = Ext_Zkr
enum clause extension = Ext_Zksed
enum clause extension = Ext_Zksh
enum clause extension = Ext_Zmmul
5 changes: 0 additions & 5 deletions model/riscv_fdext_control.sail
Original file line number Diff line number Diff line change
Expand Up @@ -15,13 +15,8 @@

/* **************************************************************** */

enum clause extension = Ext_F
function clause extensionEnabled(Ext_F) = (misa[F] == 0b1) & (mstatus[FS] != 0b00)

enum clause extension = Ext_D
function clause extensionEnabled(Ext_D) = (misa[D] == 0b1) & (mstatus[FS] != 0b00) & flen >= 64

enum clause extension = Ext_Zfinx
function clause extensionEnabled(Ext_Zfinx) = sys_enable_zfinx()

/* Floating Point CSRs */
Expand Down
4 changes: 1 addition & 3 deletions model/riscv_insts_aext.sail
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@
/* This file specifies the atomic instructions in the 'A' extension. */

/* ****************************************************************** */
enum clause extension = Ext_Zabha

function clause extensionEnabled(Ext_Zabha) = true

// Some print utils for lr/sc.
Expand Down Expand Up @@ -53,7 +53,6 @@ function amo_width_valid(size : word_width) -> bool = {
}

/* ****************************************************************** */
enum clause extension = Ext_Zalrsc
function clause extensionEnabled(Ext_Zalrsc) = misa[A] == 0b1

union clause ast = LOADRES : (bool, bool, regidx, word_width, regidx)
Expand Down Expand Up @@ -168,7 +167,6 @@ mapping clause assembly = STORECON(aq, rl, rs2, rs1, size, rd)
<-> "sc." ^ size_mnemonic(size) ^ maybe_aq(aq) ^ maybe_rl(rl) ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs2) ^ sep() ^ "(" ^ reg_name(rs1) ^ ")"

/* ****************************************************************** */
enum clause extension = Ext_Zaamo
function clause extensionEnabled(Ext_Zaamo) = misa[A] == 0b1

union clause ast = AMO : (amoop, bool, bool, regidx, regidx, word_width, regidx)
Expand Down
3 changes: 0 additions & 3 deletions model/riscv_insts_base.sail
Original file line number Diff line number Diff line change
Expand Up @@ -9,10 +9,7 @@
/* ****************************************************************** */
/* This file specifies the instructions in the base integer set. */

enum clause extension = Ext_C
function clause extensionEnabled(Ext_C) = misa[C] == 0b1

enum clause extension = Ext_Zca
function clause extensionEnabled(Ext_Zca) = extensionEnabled(Ext_C)

/* ****************************************************************** */
Expand Down
1 change: 0 additions & 1 deletion model/riscv_insts_dext.sail
Original file line number Diff line number Diff line change
Expand Up @@ -224,7 +224,6 @@ function fle_D (v1, v2, is_quiet) = {
/* **************************************************************** */
/* Helper functions for 'encdec()' */

enum clause extension = Ext_Zdinx
function clause extensionEnabled(Ext_Zdinx) = sys_enable_zfinx() & flen >= 64

function haveDoubleFPU() -> bool = extensionEnabled(Ext_D) | extensionEnabled(Ext_Zdinx)
Expand Down
2 changes: 0 additions & 2 deletions model/riscv_insts_fext.sail
Original file line number Diff line number Diff line change
Expand Up @@ -26,10 +26,8 @@
/* **************************************************************** */

// TODO: Add config flags to control Zfh and Zfhmin
enum clause extension = Ext_Zfh
function clause extensionEnabled(Ext_Zfh) = (misa[F] == 0b1) & (mstatus[FS] != 0b00)

enum clause extension = Ext_Zfhmin
// Zfhmin is a subset of Zfh. This can be changed to extensionEnabled(Ext_Zfh) | sys_enable_zfhmin() when more configuration is implemented.
function clause extensionEnabled(Ext_Zfhmin) = extensionEnabled(Ext_Zfh)

Expand Down
2 changes: 0 additions & 2 deletions model/riscv_insts_mext.sail
Original file line number Diff line number Diff line change
Expand Up @@ -11,9 +11,7 @@

/* ****************************************************************** */

enum clause extension = Ext_M
function clause extensionEnabled(Ext_M) = misa[M] == 0b1
enum clause extension = Ext_Zmmul
function clause extensionEnabled(Ext_Zmmul) = true


Expand Down
1 change: 0 additions & 1 deletion model/riscv_insts_svinval.sail
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

enum clause extension = Ext_Svinval
function clause extensionEnabled(Ext_Svinval) = sys_enable_svinval()

union clause ast = SINVAL_VMA : (regidx, regidx)
Expand Down
3 changes: 0 additions & 3 deletions model/riscv_insts_zba.sail
Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

enum clause extension = Ext_B
function clause extensionEnabled(Ext_B) = misa[B] == 0b1

enum clause extension = Ext_Zba
function clause extensionEnabled(Ext_Zba) = true | extensionEnabled(Ext_B)

/* ****************************************************************** */
Expand Down
3 changes: 0 additions & 3 deletions model/riscv_insts_zbb.sail
Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

enum clause extension = Ext_Zbb
function clause extensionEnabled(Ext_Zbb) = true | extensionEnabled(Ext_B)

enum clause extension = Ext_Zbkb
function clause extensionEnabled(Ext_Zbkb) = true

/* ****************************************************************** */
Expand Down
3 changes: 0 additions & 3 deletions model/riscv_insts_zbc.sail
Original file line number Diff line number Diff line change
Expand Up @@ -6,10 +6,7 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

enum clause extension = Ext_Zbc
function clause extensionEnabled(Ext_Zbc) = true

enum clause extension = Ext_Zbkc
function clause extensionEnabled(Ext_Zbkc) = true

/* ****************************************************************** */
Expand Down
1 change: 0 additions & 1 deletion model/riscv_insts_zbkx.sail
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

enum clause extension = Ext_Zbkx
function clause extensionEnabled(Ext_Zbkx) = true

/* ****************************************************************** */
Expand Down
1 change: 0 additions & 1 deletion model/riscv_insts_zbs.sail
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

enum clause extension = Ext_Zbs
function clause extensionEnabled(Ext_Zbs) = true | extensionEnabled(Ext_B)

/* ****************************************************************** */
Expand Down
1 change: 0 additions & 1 deletion model/riscv_insts_zcb.sail
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

enum clause extension = Ext_Zcb
function clause extensionEnabled(Ext_Zcb) = sys_enable_zcb() & extensionEnabled(Ext_Zca)

union clause ast = C_LBU : (bits(2), cregidx, cregidx)
Expand Down
1 change: 0 additions & 1 deletion model/riscv_insts_zcd.sail
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

enum clause extension = Ext_Zcd
function clause extensionEnabled(Ext_Zcd) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_D) & (xlen == 32 | xlen == 64)

union clause ast = C_FLDSP : (bits(6), regidx)
Expand Down
1 change: 0 additions & 1 deletion model/riscv_insts_zcf.sail
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,6 @@

/* ****************************************************************** */

enum clause extension = Ext_Zcf
function clause extensionEnabled(Ext_Zcf) = extensionEnabled(Ext_Zca) & extensionEnabled(Ext_F) & xlen == 32

union clause ast = C_FLWSP : (bits(6), regidx)
Expand Down
1 change: 0 additions & 1 deletion model/riscv_insts_zfa.sail
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

enum clause extension = Ext_Zfa
function clause extensionEnabled(Ext_Zfa) = true

/* FLI.H */
Expand Down
1 change: 0 additions & 1 deletion model/riscv_insts_zfh.sail
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

enum clause extension = Ext_Zhinx
function clause extensionEnabled(Ext_Zhinx) = sys_enable_zfinx()

/* **************************************************************** */
Expand Down
1 change: 0 additions & 1 deletion model/riscv_insts_zicbom.sail
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@

// Cache Block Operations - Management

enum clause extension = Ext_Zicbom
function clause extensionEnabled(Ext_Zicbom) = sys_enable_zicbom()

function cbo_clean_flush_enabled(p : Privilege) -> bool = feature_enabled_for_priv(p, menvcfg[CBCFE][0], senvcfg[CBCFE][0])
Expand Down
1 change: 0 additions & 1 deletion model/riscv_insts_zicboz.sail
Original file line number Diff line number Diff line change
Expand Up @@ -8,7 +8,6 @@

// Cache Block Operations - Zero

enum clause extension = Ext_Zicboz
function clause extensionEnabled(Ext_Zicboz) = sys_enable_zicboz()

function cbo_zero_enabled(p : Privilege) -> bool = feature_enabled_for_priv(p, menvcfg[CBZE][0], senvcfg[CBZE][0])
Expand Down
1 change: 0 additions & 1 deletion model/riscv_insts_zicond.sail
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

enum clause extension = Ext_Zicond
function clause extensionEnabled(Ext_Zicond) = true

union clause ast = ZICOND_RTYPE : (regidx, regidx, regidx, zicondop)
Expand Down
2 changes: 1 addition & 1 deletion model/riscv_insts_zifencei.sail
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@
/* This file specifies the instructions in the 'Zifencei' extension. */

/* ****************************************************************** */
enum clause extension = Ext_Zifencei

function clause extensionEnabled(Ext_Zifencei) = true

union clause ast = FENCEI : unit
Expand Down
4 changes: 1 addition & 3 deletions model/riscv_insts_zkn.sail
Original file line number Diff line number Diff line change
Expand Up @@ -10,7 +10,7 @@
* Scalar Cryptography Extension - Scalar SHA256 instructions (RV32/RV64)
* ----------------------------------------------------------------------
*/
enum clause extension = Ext_Zknh

function clause extensionEnabled(Ext_Zknh) = true

union clause ast = SHA256SIG0 : (regidx, regidx)
Expand Down Expand Up @@ -75,7 +75,6 @@ function clause execute (SHA256SUM1(rs1, rd)) = {
* ----------------------------------------------------------------------
*/

enum clause extension = Ext_Zkne
function clause extensionEnabled(Ext_Zkne) = true

union clause ast = AES32ESMI : (bits(2), regidx, regidx, regidx)
Expand Down Expand Up @@ -118,7 +117,6 @@ function clause execute (AES32ESI (bs, rs2, rs1, rd)) = {
* ----------------------------------------------------------------------
*/

enum clause extension = Ext_Zknd
function clause extensionEnabled(Ext_Zknd) = true

union clause ast = AES32DSMI : (bits(2), regidx, regidx, regidx)
Expand Down
2 changes: 0 additions & 2 deletions model/riscv_insts_zks.sail
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,6 @@
* ----------------------------------------------------------------------
*/

enum clause extension = Ext_Zksh
function clause extensionEnabled(Ext_Zksh) = true

union clause ast = SM3P0 : (regidx, regidx)
Expand Down Expand Up @@ -48,7 +47,6 @@ function clause execute (SM3P1(rs1, rd)) = {
* ----------------------------------------------------------------------
*/

enum clause extension = Ext_Zksed
function clause extensionEnabled(Ext_Zksed) = true

union clause ast = SM4ED : (bits(2), regidx, regidx, regidx)
Expand Down
3 changes: 0 additions & 3 deletions model/riscv_sys_regs.sail
Original file line number Diff line number Diff line change
Expand Up @@ -118,7 +118,6 @@ val sys_enable_zicboz = pure "sys_enable_zicboz" : unit -> bool
val sys_enable_sstc = pure "sys_enable_sstc" : unit -> bool

// Supervisor timecmp
enum clause extension = Ext_Sstc
function clause extensionEnabled(Ext_Sstc) = sys_enable_sstc()

/* This function allows an extension to veto a write to Misa
Expand Down Expand Up @@ -146,10 +145,8 @@ function clause is_CSR_defined(0x301) = true // misa
function clause read_CSR(0x301) = misa.bits
function clause write_CSR(0x301, value) = { misa = legalize_misa(misa, value); misa.bits }

enum clause extension = Ext_U
function clause extensionEnabled(Ext_U) = misa[U] == 0b1

enum clause extension = Ext_S
function clause extensionEnabled(Ext_S) = misa[S] == 0b1

/*
Expand Down
3 changes: 0 additions & 3 deletions model/riscv_types.sail
Original file line number Diff line number Diff line change
Expand Up @@ -8,9 +8,6 @@

/* Basic type and function definitions used pervasively in the model. */

/* ISA extension names as enums */
scattered enum extension

// Function used to determine if an extension is enabled in the current configuration.
// This means an extension is implemented & supported, *and* any necessary bits
// are set in the relevant CSRs (misa, mstatus, etc.) to enable its use. It is possible
Expand Down
1 change: 0 additions & 1 deletion model/riscv_vext_control.sail
Original file line number Diff line number Diff line change
Expand Up @@ -6,7 +6,6 @@
/* SPDX-License-Identifier: BSD-2-Clause */
/*=======================================================================================*/

enum clause extension = Ext_V
function clause extensionEnabled(Ext_V) = (misa[V] == 0b1) & (mstatus[VS] != 0b00)

mapping clause csr_name_map = 0x008 <-> "vstart"
Expand Down
1 change: 0 additions & 1 deletion model/riscv_zihpm.sail
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,6 @@
/*=======================================================================================*/

/* Hardware Performance Monitoring counters */
enum clause extension = Ext_Zihpm
function clause extensionEnabled(Ext_Zihpm) = true

/* Hardware performance monitoring counters */
Expand Down
1 change: 0 additions & 1 deletion model/riscv_zkr_control.sail
Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,6 @@
/*=======================================================================================*/

/* Zkr entropy seed source */
enum clause extension = Ext_Zkr
function clause extensionEnabled(Ext_Zkr) = true

/* Valid return states for reading the seed CSR. */
Expand Down

0 comments on commit 859a49c

Please sign in to comment.