Skip to content

Commit

Permalink
Make CSR definitions scattered
Browse files Browse the repository at this point in the history 
Resolve the strange split between `read_CSR` (which is not `scattered`) and `ext_read_CSR` (which is). Same for `write_CSR` and `is_CSR_defined`.

I changed the return type of `read_CSR` from `option(xlenbits)` to `xlenbits` since the code must already check `is_CSR_defined` before calling `read_CSR`. The only function that returned `None()` was the `seed` CSR in `write_seed_csr`, which actually meant you would get a weird "Unhandled write to CSR" if you wrote to `seed`.

I renamed & reordered the files slightly to make the scattered mapping work, but I haven't moved any of the actual definitions yet. In future we should actually scatter them.

Fixes riscv#410
  • Loading branch information
@Timmmm
Timmmm committed Sep 6, 2024
1 parent a58c58c commit 21bd564
Show file tree
Hide file tree
Showing 9 changed files with 306 additions and 316 deletions.
9 changes: 5 additions & 4 deletions Makefile
View file
Original file line number Diff line number Diff line change
Expand Up @@ -66,18 +66,19 @@ SAIL_DEFAULT_INST += riscv_insts_zicboz.sail
SAIL_SEQ_INST = $(SAIL_DEFAULT_INST) riscv_jalr_seq.sail
SAIL_RMEM_INST = $(SAIL_DEFAULT_INST) riscv_jalr_rmem.sail riscv_insts_rmem.sail

SAIL_SEQ_INST_SRCS = riscv_insts_begin.sail $(SAIL_SEQ_INST) riscv_insts_end.sail
SAIL_RMEM_INST_SRCS = riscv_insts_begin.sail $(SAIL_RMEM_INST) riscv_insts_end.sail
# TODO: riscv_csr_end.sail here temporarily until the scattered definitions
# are moved from riscv_insts_zicsr.sail to more appropriate places.
SAIL_SEQ_INST_SRCS = riscv_insts_begin.sail $(SAIL_SEQ_INST) riscv_insts_end.sail riscv_csr_end.sail
SAIL_RMEM_INST_SRCS = riscv_insts_begin.sail $(SAIL_RMEM_INST) riscv_insts_end.sail riscv_csr_end.sail

# System and platform sources
SAIL_SYS_SRCS = riscv_csr_map.sail
SAIL_SYS_SRCS = riscv_csr_begin.sail # Start of CSR scattered definitions.
SAIL_SYS_SRCS += riscv_vext_control.sail # helpers for the 'V' extension
SAIL_SYS_SRCS += riscv_next_regs.sail
SAIL_SYS_SRCS += riscv_sys_exceptions.sail # default basic helpers for exception handling
SAIL_SYS_SRCS += riscv_sync_exception.sail # define the exception structure used in the model
SAIL_SYS_SRCS += riscv_next_control.sail # helpers for the 'N' extension
SAIL_SYS_SRCS += riscv_softfloat_interface.sail riscv_fdext_regs.sail riscv_fdext_control.sail
SAIL_SYS_SRCS += riscv_csr_ext.sail # access to CSR extensions
SAIL_SYS_SRCS += riscv_sys_control.sail # general exception handling

# SAIL_RV32_VM_SRCS = riscv_vmem_sv32.sail riscv_vmem_rv32.sail
Expand Down
15 changes: 9 additions & 6 deletions model/riscv_csr_map.sail → model/riscv_csr_begin.sail
View file
Original file line number Diff line number Diff line change
Expand Up @@ -12,6 +12,9 @@ val csr_name_map : csreg <-> string

scattered mapping csr_name_map

// TODO: These csr_name_map definitions should be moved to the files
// corresponding to their extensions rather than all be here.

/* user trap setup */
mapping clause csr_name_map = 0x000 <-> "ustatus"
mapping clause csr_name_map = 0x004 <-> "uie"
Expand Down Expand Up @@ -190,13 +193,13 @@ overload to_str = {csr_name}

/* returns whether a CSR exists
*/
val ext_is_CSR_defined : (csreg) -> bool
scattered function ext_is_CSR_defined
val is_CSR_defined : (csreg) -> bool
scattered function is_CSR_defined

/* returns the value of the CSR if it is defined */
val ext_read_CSR : csreg -> option(xlenbits)
scattered function ext_read_CSR
val read_CSR : csreg -> xlenbits
scattered function read_CSR

/* returns new value (after legalisation) if the CSR is defined */
val ext_write_CSR : (csreg, xlenbits) -> option(xlenbits)
scattered function ext_write_CSR
val write_CSR : (csreg, xlenbits) -> xlenbits
scattered function write_CSR
18 changes: 12 additions & 6 deletions model/riscv_csr_ext.sail → model/riscv_csr_end.sail
View file
Original file line number Diff line number Diff line change
Expand Up @@ -14,11 +14,17 @@ end csr_name_map
previously. */
function csr_name(csr) = csr_name_map(csr)

function clause ext_is_CSR_defined(_) = false
end ext_is_CSR_defined
function clause is_CSR_defined(_) = false
end is_CSR_defined

function clause ext_read_CSR _ = None()
end ext_read_CSR
function clause read_CSR(csr) = {
// This should be impossible because is_CSR_defined() should have returned false.
internal_error(__FILE__, __LINE__, "Read from CSR that does not exist: " ^ bits_str(csr));
}
end read_CSR

function clause ext_write_CSR (_, _) = None()
end ext_write_CSR
function clause write_CSR(csr, _) = {
// This should be impossible because is_CSR_defined() should have returned false.
internal_error(__FILE__, __LINE__, "Write to CSR that does not exist: " ^ bits_str(csr));
}
end write_CSR
20 changes: 10 additions & 10 deletions model/riscv_fdext_control.sail
View file
Original file line number Diff line number Diff line change
Expand Up @@ -24,18 +24,18 @@ function clause extensionEnabled(Ext_D) = (misa[D] == 0b1) & (mstatus[FS] != 0b0
enum clause extension = Ext_Zfinx
function clause extensionEnabled(Ext_Zfinx) = sys_enable_zfinx()

/* val clause ext_is_CSR_defined : (csreg) -> bool */
/* val clause is_CSR_defined : (csreg) -> bool */

function clause ext_is_CSR_defined (0x001) = extensionEnabled(Ext_F) | extensionEnabled(Ext_Zfinx)
function clause ext_is_CSR_defined (0x002) = extensionEnabled(Ext_F) | extensionEnabled(Ext_Zfinx)
function clause ext_is_CSR_defined (0x003) = extensionEnabled(Ext_F) | extensionEnabled(Ext_Zfinx)
function clause is_CSR_defined (0x001) = extensionEnabled(Ext_F) | extensionEnabled(Ext_Zfinx)
function clause is_CSR_defined (0x002) = extensionEnabled(Ext_F) | extensionEnabled(Ext_Zfinx)
function clause is_CSR_defined (0x003) = extensionEnabled(Ext_F) | extensionEnabled(Ext_Zfinx)

function clause ext_read_CSR (0x001) = Some(zero_extend(fcsr[FFLAGS]))
function clause ext_read_CSR (0x002) = Some(zero_extend(fcsr[FRM]))
function clause ext_read_CSR (0x003) = Some(zero_extend(fcsr.bits))
function clause read_CSR (0x001) = zero_extend(fcsr[FFLAGS])
function clause read_CSR (0x002) = zero_extend(fcsr[FRM])
function clause read_CSR (0x003) = zero_extend(fcsr.bits)

function clause ext_write_CSR (0x001, value) = { ext_write_fcsr(fcsr[FRM], value[4..0]); Some(zero_extend(fcsr[FFLAGS])) }
function clause ext_write_CSR (0x002, value) = { ext_write_fcsr(value[2..0], fcsr[FFLAGS]); Some(zero_extend(fcsr[FRM])) }
function clause ext_write_CSR (0x003, value) = { ext_write_fcsr(value[7..5], value[4..0]); Some(zero_extend(fcsr.bits)) }
function clause write_CSR (0x001, value) = { ext_write_fcsr(fcsr[FRM], value[4..0]); zero_extend(fcsr[FFLAGS]) }
function clause write_CSR (0x002, value) = { ext_write_fcsr(value[2..0], fcsr[FFLAGS]); zero_extend(fcsr[FRM]) }
function clause write_CSR (0x003, value) = { ext_write_fcsr(value[7..5], value[4..0]); zero_extend(fcsr.bits) }

/* **************************************************************** */
Loading

0 comments on commit 21bd564

Please sign in to comment.