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Updating the memory mapping for SocDemo #117

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merged 1 commit into from
Jul 17, 2024

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Bill94l
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@Bill94l Bill94l commented Jul 16, 2024

Hi,

Updated memory mapping for SocDemo to avoid the failure of nax/machine code with SocSim

Thanks :D

@Dolu1990 Dolu1990 merged commit d6115eb into SpinalHDL:main Jul 17, 2024
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@Dolu1990
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Thanks ^^

@Dolu1990
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Next week i will be gone in holiday, let's me know if you need me to take care of anohter issue / PR before i'm gone XD

@Bill94l
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Bill94l commented Jul 17, 2024

  • I'm preparing a pull request to check that Rd or Rs is not equal to zero for compressed instructions that require checking. As soon as I'm done, I'll let you know.
  • If you validate the solution atkarim offers in this issue Nax not trap on store fault #116 (comment), we already have a pull request ready which validates all the regression tests.

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If you validate the solution atkarim

I answerd it just now.
In short, a simple workaround may just be to define every thing which isn't cachable as part of the ioRegion, including non existing region ^^
Then maybe the testbench will scream on you for trying to read non-existing region, but that would be single line fix to make the testbench returning fault on those case.

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