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Dolu1990 committed Oct 13, 2023
1 parent 8124eb4 commit fb575af
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Showing 3 changed files with 80 additions and 5 deletions.
2 changes: 1 addition & 1 deletion ext/NaxSoftware
Submodule NaxSoftware updated 35 files
+0 −1 baremetal/coherency/.gitignore
+0 −3 baremetal/coherency/makefile
+0 −821 baremetal/coherency/src/crt.S
+0 −1 baremetal/coherency_burst/.gitignore
+0 −3 baremetal/coherency_burst/makefile
+0 −736 baremetal/coherency_burst/src/crt.S
+1 −1 baremetal/driver/sim_asm.h
+ baremetal/machine/build/rv32ima/machine.elf
+ baremetal/machine/build/rv32imac/machine.elf
+ baremetal/machine/build/rv32imaf/machine.elf
+ baremetal/machine/build/rv32imafc/machine.elf
+ baremetal/machine/build/rv32imafd/machine.elf
+ baremetal/machine/build/rv32imafdc/machine.elf
+ baremetal/machine/build/rv64ima/machine.elf
+ baremetal/machine/build/rv64imac/machine.elf
+ baremetal/machine/build/rv64imaf/machine.elf
+ baremetal/machine/build/rv64imafc/machine.elf
+ baremetal/machine/build/rv64imafd/machine.elf
+ baremetal/machine/build/rv64imafdc/machine.elf
+2 −2 baremetal/machine/src/crt.S
+0 −1 baremetal/pulling_ordering/.gitignore
+0 −3 baremetal/pulling_ordering/makefile
+0 −639 baremetal/pulling_ordering/src/crt.S
+2 −2 buildroot/boards/naxriscv_sim/opensbi/platform.c
+0 −0 debian/README.md
+0 −0 debian/linux/config-virt
+ debian/linux/linux.dtb
+0 −0 debian/linux/linux.dts
+0 −0 debian/opensbi/config.mk
+0 −0 debian/opensbi/objects.mk
+2 −2 debian/opensbi/platform.c
+0 −286 debian_litex/README.md
+0 −3,758 debian_litex/linux/.config
+0 −5 debian_litex/p1/boot.json
+0 −170 debian_litex/p1/linux.dts
8 changes: 4 additions & 4 deletions src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala
Original file line number Diff line number Diff line change
Expand Up @@ -33,7 +33,7 @@ object SocSim extends App {
// hub.parameter.cacheBytes = 4096
// icache.cacheSize = 2048
}
val compiled = sc.compile(new SocDemoSim(4))
val compiled = sc.compile(new SocDemoSim(2))

// for (i <- 0 until 64) test("test_" + i) {
// compiled.doSimUntilVoid(name = s"test_$i", seed = i)(testIt(_))
Expand Down Expand Up @@ -142,10 +142,10 @@ object SocSim extends App {
// val elf = new Elf(new File("ext/NaxSoftware/baremetal/dhrystone/build/rv32ima/dhrystone.elf"))
// val elf = new Elf(new File("ext/NaxSoftware/baremetal/coremark/build/rv32ima/coremark.elf"))
// val elf = new Elf(new File("ext/NaxSoftware/baremetal/freertosDemo/build/rv32ima/freertosDemo.elf"))
// val elf = new Elf(new File("ext/NaxSoftware/baremetal/play/build/rv32ima/play.elf"))
val elf = new Elf(new File("ext/NaxSoftware/baremetal/play/build/rv32ima/play.elf"))
// val elf = new Elf(new File("ext/NaxSoftware/baremetal/simple/build/rv32ima/simple.elf"))
// val elf = new Elf(new File("ext/NaxSoftware/baremetal/coherency/build/rv32ima/coherency.elf"))
val elf = new Elf(new File("ext/NaxSoftware/baremetal/coherency_burst/build/rv32ima/coherency_burst.elf"))
// val elf = new Elf(new File("ext/NaxSoftware/baremetal/coherency_burst/build/rv32ima/coherency_burst.elf"))
// val elf = new Elf(new File("ext/NaxSoftware/baremetal/pulling_ordering/build/rv32ima/pulling_ordering.elf"))
// val elf = new Elf(new File("ext/NaxSoftware/baremetal/machine/build/rv32ima/machine.elf"))
Expand All @@ -169,7 +169,7 @@ object SocSim extends App {
}
}
*/
//

memAgent.mem.loadBin(0x00000000l, "ext/NaxSoftware/buildroot/images/rv32ima/fw_jump.bin")
memAgent.mem.loadBin(0x00400000l, "ext/NaxSoftware/buildroot/images/rv32ima/Image")
memAgent.mem.loadBin(0x01000000l, "ext/NaxSoftware/buildroot/images/rv32ima/rootfs.cpio")
Expand Down
75 changes: 75 additions & 0 deletions src/main/scala/naxriscv/utilities/Misc.scala
Original file line number Diff line number Diff line change
Expand Up @@ -61,6 +61,81 @@ object MulSpliter{
}
}

//object MulAggregator{
// case class Splits(offset : Int, width : Int, budget : Int, var id : Int = 0, from : Seq[Int]){
//
// }
//
// def apply(splits : Seq[Splits], widthMax : Int, srcsMax : Int) = {
// var srcs = splits.sortBy(_.offset).toList
// val works = ArrayBuffer[Splits]()
// srcs ++= splits
// for((e,i) <- srcs.zipWithIndex) e.id = i
//
// while(srcs.size >= 2) {
// /* var elements = srcs.take(srcsMax)
// val a = elements(0)
// val b = elements(1)
// if(a.offset != b.offset){
// //Bad seed
// assert(a.offset < b.offset)
// val frontPadding = b.offset - a.offset
// if(frontPadding >= a.width){
// works += a.copy(from = List(a.id))
// srcs = srcs.tail
// } else {
// works += a.copy(width = frontPadding, from = List(a.id))
// srcs = a.copy(offset = b.offset, width = a.width-frontPadding) :: srcs.tail
// }
// } else {
// val offset = a.offset
// val endMax = offset + widthMax
// elements = elements.filter(_.offset < endMax)
//
// if (a.offset + a.width <= adderOffset) {
// //'a' is completly isolated
// works += a.copy(from = List(a.id))
// srcs = srcs.tail
// } else {
// val frontPadding = b.offset - a.offset
// if (frontPadding != 0) {
// works += a.copy(width = frontPadding, from = List(a.id))
// }
// // val adderWidth = widthMax :: elements.map(e => e.offset +
//
// }
// }*/
// srcs = srcs.sortBy(_.offset)
// val a = srcs(0)
// val b = srcs(1)
//
// if(a.offset + a.width <= b.offset){
// works += a.copy(from = List(a.id))
// srcs = srcs.tail
// } else {
// val frontPadding = b.offset - a.offset
// if (frontPadding != 0) {
// works += a.copy(width = frontPadding, from = List(a.id))
// }
// val adderWidth = List(a.width-frontPadding, b.width, widthMax).min
// works += Splits(offset = b.offset, width = adderWidth, from = List(a.id, b.id))
// if(adderWidth != b.width){
// srcs = b.copy(offset = b.offset + adderWidth, width = b.width - adderWidth) :: srcs
// }
// if(frontPadding + adderWidth != a.width){
// srcs = a.copy(offset = a.offset + frontPadding + adderWidth, width = a.width - frontPadding - adderWidth) :: srcs
// }
// }
// }
//
// if(srcs.nonEmpty) {
// works += srcs.head.copy(from = List(srcs.head.id))
// }
//
// works
// }
//}

trait WithRfWriteSharedSpec{
case class RfWriteSharingSpec(key : Any, withReady : Boolean, priority : Int)
private val rfWriteSharing = mutable.LinkedHashMap[RegfileSpec, RfWriteSharingSpec]()
Expand Down

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