litex fix cache parameters

SpinalHDL · Oct 12, 2023 · 9e44c1b · 9e44c1b
1 parent 2948aa4
commit 9e44c1b
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Showing 3 changed files with 4 additions and 11 deletions.
diff --git a/src/main/scala/naxriscv/platform/litex/NaxGen.scala b/src/main/scala/naxriscv/platform/litex/NaxGen.scala
@@ -37,16 +37,10 @@ case class LitexMemoryRegion(mapping : SizeMapping, mode : String, bus : String)
 // python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=naxriscv  --bus-standard axi-lite --with-video-framebuffer --with-coherent-dma --with-sdcard --with-ethernet --scala-args='alu-count=1,decode-count=1' --with-jtag-tap --sys-clk-freq 50000000 --cpu-count 1 --soc-json build/digilent_nexys_video/csr.json --build --load
 //
 //Debian
-//python3 -m litex_boards.targets.digilent_nexys_video --cpu-type=naxriscv  --bus-standard axi-lite --with-video-framebuffer --with-coherent-dma --with-sdcard --with-ethernet --xlen=64 --scala-args='rvc=true,rvf=true,rvd=true,alu-count=2,decode-count=2'  --with-jtag-tap --sys-clk-freq 100000000 --cpu-count 2 --soc-json build/digilent_nexys_video/csr.json --update-repo no --load
+//python3 -m litex_boards.targets.diŝgilent_nexys_video --cpu-type=naxriscv  --bus-standard axi-lite --with-video-framebuffer --with-coherent-dma --with-sdcard --with-ethernet --xlen=64 --scala-args='rvc=true,rvf=true,rvd=true,alu-count=2,decode-count=2'  --with-jtag-tap --sys-clk-freq 100000000 --cpu-count 2 --soc-json build/digilent_nexys_video/csr.json --update-repo no --load
 //litex_sim --cpu-type=naxriscv  --with-sdram --sdram-data-width=64 --bus-standard axi-lite  --scala-args='rvc=true,rvf=true,rvd=true,alu-count=1,decode-count=1' --with-coherent-dma --xlen=64 --trace-fst --sdram-init boot.json
 
-//TODO :
-/*
-- Directory probe parameter handeling
-- NaxRiscv support for tilelink probe perm
-- directory writebackend reschedules optimizations
-- FMax
- */
+
 object NaxGen extends App{
   var netlistDirectory = "."
   var netlistName = "NaxSoc"

diff --git a/src/main/scala/naxriscv/platform/litex/NaxSoc.scala b/src/main/scala/naxriscv/platform/litex/NaxSoc.scala
@@ -81,8 +81,8 @@ class NaxSoc(c : NaxSocConfig) extends Component{
 
   val l2 = withL2 generate new Area {
     val cache = new CacheFiber()
-    cache.parameter.cacheWays = 4
-    cache.parameter.cacheBytes = 128 * 1024
+    cache.parameter.cacheWays = l2Ways
+    cache.parameter.cacheBytes = l2Bytes
     cache.up << memFilter.down
     cache.up.setUpConnection(a = StreamPipe.FULL, c = StreamPipe.FULL)
     cache.down.forceDataWidth(mainDataWidth)

diff --git a/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala b/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala
@@ -90,7 +90,6 @@ object SocSim extends App {
 
     val memAgent = new MemoryAgent(dut.mem.node.bus, cd, seed = 0, randomProberFactor = 0.2f)(null) {
       mem.randOffset = 0x80000000l
-//      randomProberFactor = 2.0f //TODO remove me
 
       import driver.driver._