cleanup

SpinalHDL · Oct 16, 2023 · 8b8a72c · 8b8a72c
1 parent 7776f6c
commit 8b8a72c
Showing 1 changed file with 0 additions and 1 deletion.
diff --git a/src/main/scala/naxriscv/lsu/DataCache.scala b/src/main/scala/naxriscv/lsu/DataCache.scala
@@ -692,7 +692,6 @@ case class DataCacheParameters(cacheSize: Int,
   def toTilelinkS2mSupported(proposed : S2mSupport) = S2mSupport(S2mTransfers(probe = SizeRange(lineSize)))
 }
 
-//TODO L1 status tracking into L2 need to be exact, so need to notify when going from shared to invalid/another line.
 class DataCache(val p : DataCacheParameters) extends Component {
   import p._