litex add l2 parameters

SpinalHDL · Oct 11, 2023 · 4da1cd8 · 4da1cd8
1 parent a7cf555
commit 4da1cd8
Show file tree

Hide file tree

Showing 3 changed files with 40 additions and 23 deletions.
diff --git a/src/main/scala/naxriscv/platform/litex/NaxGen.scala b/src/main/scala/naxriscv/platform/litex/NaxGen.scala
@@ -74,6 +74,8 @@ object NaxGen extends App{
     opt[Unit]("with-jtag-tap") action  { (v, c) => withJtagTap = true }
     opt[Unit]("with-jtag-instruction") action  { (v, c) => withJtagInstruction = true }
     opt[Unit]("with-debug") action { (v, c) => withDebug = true }
+    opt[Int]("l2-bytes") action { (v, c) => l2Bytes = v }
+    opt[Int]("l2-ways") action { (v, c) => l2Ways = v }
     opt[Unit]("with-dma") action { (v, c) => withDma = true }
     opt[Seq[String]]("memory-region") unbounded() action  { (v, c) =>
       assert(v.length == 4, "--memory-region need 4 parameters")

diff --git a/src/main/scala/naxriscv/platform/litex/NaxSoc.scala b/src/main/scala/naxriscv/platform/litex/NaxSoc.scala
@@ -30,6 +30,9 @@ class NaxSocConfig(){
   var withDebug = false
   var withDma = false
   var mBusWidth = 64
+  var l2Bytes = 128*1024
+  var l2Ways = 8
+  def withL2 = l2Bytes > 0
 }
 
 class NaxSoc(c : NaxSocConfig) extends Component{
@@ -66,29 +69,41 @@ class NaxSoc(c : NaxSocConfig) extends Component{
     memFilter.up << bridge.down
   }
 
-//  val hub = new HubFiber()
-  val hub = new DirectoryFiber()
-  hub.parameter.cacheWays = 4
-  hub.parameter.cacheBytes = 128 * 1024
-  hub.up << memFilter.down
-  hub.up.setUpConnection(a = StreamPipe.FULL, c = StreamPipe.FULL)
-  hub.down.forceDataWidth(mainDataWidth)
+
+  var nonCoherent : Node = null
+  val noL2 = !withL2 generate new Area {
+    val hub = new HubFiber()
+    hub.up << memFilter.down
+    hub.up.setUpConnection(a = StreamPipe.FULL, c = StreamPipe.FULL)
+    hub.down.forceDataWidth(mainDataWidth)
+    nonCoherent = hub.down
+  }
+
+  val l2 = withL2 generate new Area {
+    val cache = new DirectoryFiber()
+    cache.parameter.cacheWays = 4
+    cache.parameter.cacheBytes = 128 * 1024
+    cache.up << memFilter.down
+    cache.up.setUpConnection(a = StreamPipe.FULL, c = StreamPipe.FULL)
+    cache.down.forceDataWidth(mainDataWidth)
+    nonCoherent = cache.down
+  }
 
   val withMem = regions.exists(_.onMemory)
   val toAxi4 = withMem generate new fabric.Axi4Bridge
   if(withMem) {
     toAxi4.up.forceDataWidth(mBusWidth)
     toAxi4.down.addTag(PMA.MAIN)
     regions.filter(_.onMemory).foreach(r =>
-      toAxi4.up at r.mapping of hub.down
+      toAxi4.up at r.mapping of nonCoherent
     )
   }
 
 
 
   val peripheral = new Area {
     val bus = Node()
-    bus << (hub.down, ioFilter.down)
+    bus << (nonCoherent, ioFilter.down)
     bus.setDownConnection(a = StreamPipe.HALF, d = StreamPipe.HALF)
     bus.forceDataWidth(32)
 

diff --git a/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala b/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala
@@ -29,8 +29,8 @@ object SocSim extends App {
     val dcache = naxes(0).plugins.collectFirst { case p: DataCachePlugin => p }.get
     val icache = naxes(0).plugins.collectFirst { case p: FetchCachePlugin => p }.get
 
-    dcache.cacheSize = 2048
-    hub.parameter.cacheBytes = 4096
+//    dcache.cacheSize = 2048
+//    hub.parameter.cacheBytes = 4096
 //    icache.cacheSize = 2048
   }
   val compiled = sc.compile(new SocDemoSim(4))
@@ -138,7 +138,7 @@ object SocSim extends App {
       }
     }
 
-
+/*
 
 //            val elf = new Elf(new File("ext/NaxSoftware/baremetal/dhrystone/build/rv32ima/dhrystone.elf"))
 //              val elf = new Elf(new File("ext/NaxSoftware/baremetal/coremark/build/rv32ima/coremark.elf"))
@@ -169,18 +169,18 @@ object SocSim extends App {
             if (pc == failSymbol) delayed(1)(simFailure("Software reach the fail symbole :("))
           }
         }
-
-//
-//    memAgent.mem.loadBin(0x00000000l, "ext/NaxSoftware/buildroot/images/rv32ima/fw_jump.bin")
-//    memAgent.mem.loadBin(0x00400000l, "ext/NaxSoftware/buildroot/images/rv32ima/Image")
-//    memAgent.mem.loadBin(0x01000000l, "ext/NaxSoftware/buildroot/images/rv32ima/rootfs.cpio")
-//    memAgent.mem.loadBin(0x00F80000l, s"ext/NaxSoftware/buildroot/images/rv32ima/linux_${dut.naxes.size}c.dtb")
+*/
 //
-//
-//    tracer.loadBin(0x80000000l, new File("ext/NaxSoftware/buildroot/images/rv32ima/fw_jump.bin"))
-//    tracer.loadBin(0x80F80000l, new File(s"ext/NaxSoftware/buildroot/images/rv32ima/linux_${dut.naxes.size}c.dtb"))
-//    tracer.loadBin(0x80400000l, new File("ext/NaxSoftware/buildroot/images/rv32ima/Image"))
-//    tracer.loadBin(0x81000000l, new File("ext/NaxSoftware/buildroot/images/rv32ima/rootfs.cpio"))
+    memAgent.mem.loadBin(0x00000000l, "ext/NaxSoftware/buildroot/images/rv32ima/fw_jump.bin")
+    memAgent.mem.loadBin(0x00400000l, "ext/NaxSoftware/buildroot/images/rv32ima/Image")
+    memAgent.mem.loadBin(0x01000000l, "ext/NaxSoftware/buildroot/images/rv32ima/rootfs.cpio")
+    memAgent.mem.loadBin(0x00F80000l, s"ext/NaxSoftware/buildroot/images/rv32ima/linux_${dut.naxes.size}c.dtb")
+
+
+    tracer.loadBin(0x80000000l, new File("ext/NaxSoftware/buildroot/images/rv32ima/fw_jump.bin"))
+    tracer.loadBin(0x80F80000l, new File(s"ext/NaxSoftware/buildroot/images/rv32ima/linux_${dut.naxes.size}c.dtb"))
+    tracer.loadBin(0x80400000l, new File("ext/NaxSoftware/buildroot/images/rv32ima/Image"))
+    tracer.loadBin(0x81000000l, new File("ext/NaxSoftware/buildroot/images/rv32ima/rootfs.cpio"))
 
     println("Sim starting <3")
     //      cd.waitSampling(4000000)