PCE: Block vram accesses at the start of horizontal sync

Makes timing test rom results match hardware a bit better
SourMesen · Dec 23, 2023 · d3a6aad · d3a6aad
1 parent 0cb1c2b
commit d3a6aad
Show file tree

Hide file tree

Showing 2 changed files with 13 additions and 1 deletion.
diff --git a/Core/PCE/PceVdc.cpp b/Core/PCE/PceVdc.cpp
@@ -201,6 +201,7 @@ void PceVdc::SetHorizontalMode(PceVdcModeH hMode)
 			_loadBgStart = UINT16_MAX;
 			_evalStartCycle = UINT16_MAX;
 			_hModeCounter = DotsToClocks((_state.HvLatch.HorizSyncWidth + 1) * 8);
+			_hSyncStartClock = _console->GetMasterClock();
 			ProcessHorizontalSyncStart();
 			//LogDebug("H: " + std::to_string(_state.HClock) + " - HSW");
 			break;
@@ -728,7 +729,11 @@ void PceVdc::ProcessEndOfScanline()
 
 	//VCE sets HBLANK to low every 1365 clocks, interrupting what 
 	//the VDC was doing and starting a HSW phase
-	_hMode = PceVdcModeH::Hsw;
+	if(_hMode != PceVdcModeH::Hsw) {
+		_hMode = PceVdcModeH::Hsw;
+		_hSyncStartClock = _console->GetMasterClock();
+	}
+
 	_loadBgStart = UINT16_MAX;
 	_evalStartCycle = UINT16_MAX;
 
@@ -971,6 +976,11 @@ void PceVdc::ProcessVramAccesses()
 	}
 
 	if(!accessBlocked) {
+		if(_hMode == PceVdcModeH::Hds && _console->GetMasterClock() - _hSyncStartClock < 8 * GetClockDivider()) {
+			//VRAM accesses appear to be blocked during the first 8 dots of horizontal sync
+			return;
+		}
+
 		if(_pendingMemoryRead) {
 			ProcessVramRead();
 		} else if(_pendingMemoryWrite) {
@@ -1337,6 +1347,7 @@ void PceVdc::Serialize(Serializer& s)
 
 		SV(_nextEvent);
 		SV(_nextEventCounter);
+		SV(_hSyncStartClock);
 
 		SV(_drawSpriteCount);
 		SV(_totalSpriteCount);

diff --git a/Core/PCE/PceVdc.h b/Core/PCE/PceVdc.h
@@ -107,6 +107,7 @@ class PceVdc final : public ISerializable
 
 	PceVdcEvent _nextEvent = PceVdcEvent::None;
 	uint16_t _nextEventCounter = 0;
+	uint64_t _hSyncStartClock = 0;
 
 	bool _isVdc2 = false;
 	MemoryType _vramType = MemoryType::PceVideoRam;