Pinned Loading

1. crossing_clock_domains_HDL_sync-ack crossing_clock_domains_HDL_sync-ack Public

   This module is a clock speed agnostic domain snychroniser. A valid_in pulse is passed between clock domains. Busy signal is used for further flow control.

   Verilog

2. Thesis-RNG Thesis-RNG Public

   Implementation and evaluation of FPGA RNG via oscillating rings against NIST 800-22 Tests

3. Pipe-FPGA-Func-Gen-Bram Pipe-FPGA-Func-Gen-Bram Public

   Pipelined Function Generator for FPGA using block ram. DAC uses PWM to output wave form.

   VHDL

4. LED-Matrix-Wifi-Games LED-Matrix-Wifi-Games Public

   A 30x30 LED Matrix, which contains a collection of games, driven by ESP32 using RTOS operating system. Played with andriod/ios phones over wifi.

   C++

5. HAL_Atmega328p_bare_metal HAL_Atmega328p_bare_metal Public

   Hardware abstraction layer, which configures hardware timers of Atmega328p. Set interrupt type and length from command line.

   C

6. Reset-Synchroniser-in-Verilog Reset-Synchroniser-in-Verilog Public

   De-asserting an asynchronous reset signal can cause metastability. This module fixes that, by synchronising the de-assertion of the reset.

   Verilog