SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility

1. Overview

SAGERoute takes circuit netlist, technology file and user defined config as input to generate the high-quality solution for analog circuit.

2. Input Parameters

techfile:    Basic information of technology lib. Here we release a mock PDK for your test.
paramfile:   Some parameters for user to directly control the routing kernel.
netlist:     A formal netlist generated from CDF file.
placement:   Here we only release the placement generated by automatic tools (device coordinates only). The manual placement (GDSII format) cannot be realeased due to the NDA.
placement_gds: Optional. Tagged placement in GDSII format.
constraints: Optional. The electric current information of the circuit.
result:      You could save the result in GDSII format here.

2. Compilation Platform

Operating system:  Ubuntu 18.04 
GCC version:  7.5.0
Runtime dependency: Lpsolve5.5 (liblpsolve55.so), libz.so, libm.so, libc.so, libdl.so

3. Run to the Program

To use netlist and placement as input you should use the following command

./sageroute \ 
--techfile="../benchmark/mockPDK/lef.json"  \
--paramfile="../benchmark/ota2/config.json" \ 
--netlist="../benchmark/ota2/ota2.sp"       \
--placement="../benchmark/ota2/ota2.json"   \
--constraints="../benchmark/ota2/elec.json" \
--result="../benchmark/ota2/ota2.gds"         

To use the tagged manual placement (GDSII format), you should use the following commad:

./sageroute \
--techfile="../benchmark/mockPDK/lef.json" \
--paramfile="../benchmark/ota2/config.json" \
--placement_gds="YOUR_TAGGED_PLACEMENT.gds" \
--constraints="../benchmark/ota2/elec.json" \
--result="../benchmark/ota2/ota2.gds"

Note that the first mode only supprts a particular technology node, because the device of mode1 are generated by MAGICAL device generater. The placement_gds in mode2 contains more information including the device structure, which is very different from the basic placement file in mode1 We provide a testcase for mode1. However we can't provide gds case for mode2 due to NDA. You should prepare the placement_gds following the next step

4. Preparation of Tagged GDSII for Placement

If you want to use the routing with the manual GDSII input, please prepare the GDSII according to the following steps:

1. TAG all of the pins with correct net name, note that the router will connect the pins with the same net name. (TAG is on the Metal layer not the pin layer)
2. Select correct routing layer in config.json
3. Set the bLayoutparse to true.

Here is an example of a tagged GDSII file:

5. Citation

@inproceedings{zhang2023sageroute,
    author = {Zhang, Haoyi and Gao, Xiaohan and Luo, Haoyang and Song, Jiahao and Liu, Junhua and Tang, Xiyuan and Lin, Yibo and Wang, Runsheng and Huang, Ru},
    title = {SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design Compatibility},
    booktitle = {IEEE/ACM Proceedings Design, Automation and Test in Eurpoe (DATE)},
    year = {2023},
    numpages = {6},
    location = {Antwerp, Belgium},
}

6. Contact

If you have any questions, please do not hesitate to contact us or raise issues on Github.

Haoyi Zhang: [email protected]