config: add config for paddr_bits and mmu_capability · OpenXiangShan/riscv-isa-sim@4b423ba

Triggered via pull request August 16, 2024 02:34

cebarobot

opened #28

difftest-sv48

Status Success

Total duration 5m 33s

Artifacts 3

build-difftest-so.yml

on: pull_request

Matrix: Build spike-so for difftest

Produced during runtime

Name	Size
riscv64-nutshell-spike-so Expired	1.95 MB
riscv64-rocket_chip-spike-so Expired	1.95 MB
riscv64-xiangshan-spike-so Expired	1.95 MB