CI: fix CI

OpenXiangShan · Jan 8, 2025 · c674bc8 · c674bc8
1 parent be30ea6
commit c674bc8
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Showing 2 changed files with 2 additions and 3 deletions.
diff --git a/.github/workflows/main.yml b/.github/workflows/main.yml
@@ -306,7 +306,6 @@ jobs:
             make simv VCS=verilator -j2
             ./build/simv +workload=$WORKLOAD +b=0 +e=-1 +diff=$REF_SO +max-instrs=5000 +warmup_instr=1000
             make clean
-            ./build/simv +workload=./ready-to-run/microbench.bin +b=0 +e=-1 +diff=./ready-to-run/riscv64-nemu-interpreter-so +max-instrs=5000 +warmup_instr=1000
 
   test-difftest-fpga:
     runs-on: ubuntu-22.04
@@ -344,4 +343,4 @@ jobs:
             make clean
             make sim-verilog MILL_ARGS="--difftest-config SF" -j2
             cd ./difftest
-            make fpga-build WITH_CHISELDB=0 WITH_CONSTANTIN=0
+            make fpga-build FPGA=1
diff --git a/src/test/csrc/fpga/xdma_unpack.cpp b/src/test/csrc/fpga/xdma_unpack.cpp
@@ -13,9 +13,9 @@
 *
 * See the Mulan PSL v2 for more details.
 ***************************************************************************************/
+#include "xdma_unpack.h"
 #include "diffstate.h"
 #include "difftest-dpic.h"
-#include "squash_unpack.h"
 #include <assert.h>
 #include <cstdio>
 #include <string.h>