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Pull requests: OpenXiangShan/Utility
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fix(ClockGateReg): using apply1bitGate to add clock gate to 1-bit valid signal
#92
opened Dec 17, 2024 by
sinceforYy
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feat(SRAM): use
ValName for better and steady naming
#84
opened Oct 31, 2024 by
Tang-Haojin
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ChiselDB: dynamically append hartid for table name and site name
#45
opened Nov 6, 2023 by
Tang-Haojin
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