arch-riscv: fix hpmCounter logic

[happy-lx]

• when privilege mode is U, corresponding hpm counter can be read only when corresponding bit of scounteren and mcounteren are both set.
• make scounteren writeable

Change-Id: Ia8332471232db9a2b2ce732ea74dae6497428eef

[eastonman]

I have met a very similar problem recently.
MCOUNTEREN is writable and NEMU riscv64-gem5-ref_defconfig sets Zihpm and Zictr off, resulting in difftest error.

After allowing {M,S,H}COUNTEREN to be writable and turning Zihpm Zictr on, no difftest error happens. However, some checkpoints print opensbi trap messages which indicates more problems.

Do you have any idea about this?

[happy-lx]

I have met a very similar problem recently. MCOUNTEREN is writable and NEMU riscv64-gem5-ref_defconfig sets Zihpm and Zictr off, resulting in difftest error. After allowing {M,S,H}COUNTEREN to be writable and turning Zihpm Zictr on, no difftest error happens.

yes, I have met very similar things before, I think these options should be turned on in NEMU

However, some checkpoints print opensbi trap messages which indicates more problems.

Do you have any idea about this?

I also encountered an opensbi trap problem. Later I found out that it was because reading the time csr on gem5 would always trigger illegal Instruction fault. I’m not sure if you are in a similar situation.

GEM5/src/arch/riscv/isa/formats/standard.isa

Lines 365 to 371 in d46d2c5

	case CSR_TIME: {
	std::string error = csprintf(
	"force accessing to time CSR generate fault\n");
	olddata = 0;
	return std::make_shared<IllegalInstFault>(error, machInst);
	break;
	}

[eastonman]

@happy-lx Yes, my opensbi trap problem is the same as yours.

[eastonman]

Ok, the code LGTM