mem: non-piped L2,L3 and split slices

Change-Id: Ie2d4f0fd1bec142bd3b2877bfb9477fc160f8b6b

src/mem/cache/Cache.py

@@ -153,6 +153,7 @@ class BaseCache(ClockedObject):
     cache_level = Param.Unsigned(0, "Cache level (L1 is 1, L2 is 2, etc.)")
 
     tag_load_read_ports = Param.Unsigned(3, "Total tag read ports for load/prefetcher(in L1 Cache)")
+    slice_num = Param.Int(4, "slice number (-1 is disable)")
 
     force_hit = Param.Bool(False, "Force some PC to hit in L1")
     way_entries = Param.MemorySize(

src/mem/cache/base.cc

@@ -110,6 +110,7 @@ BaseCache::BaseCache(const BaseCacheParams &p, unsigned blk_size)
       writeBuffer("write buffer", p.write_buffers, p.mshrs, p.name),
       tags(p.tags),
       tagLoadReadPorts(p.tag_load_read_ports),
+      sliceNum(p.slice_num),
       freeTagLoadReadPorts(p.tag_load_read_ports),
       lastTagAccessCheckCycle(0),
       compressor(p.compressor),
@@ -178,6 +179,12 @@ BaseCache::BaseCache(const BaseCacheParams &p, unsigned blk_size)
     if (compressor)
         compressor->setCache(this);
 
+    if (sliceNum > 0) {
+        sliceReadyTick.resize(sliceNum, 0);
+        assert(popCount(sliceNum) == 1);
+    }
+
+
     if (dumpMissPC && cacheLevel) {
         registerExitCallback([this]() {
             if (pcMissCount.empty())
@@ -371,15 +378,19 @@ BaseCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time, b
         // just as the value of lat overriden by access(), which calls
         // the calculateAccessLatency() function.
         DPRINTF(Cache, "In handle timing hit, pkt has data: %i\n", pkt->hasData());
-        if (cacheLevel == 1 && pkt->isRead()) {
-            assert(pkt->hasData());
+        if (cacheLevel == 1) {
             // load pipe shoud have fixed delay
             this->schedule(new SendTimingRespEvent(this, pkt), request_time - 1);
         }
         else {
-            cpuSidePort.schedTimingResp(pkt, request_time);
+            Tick delay = calculateBusyLatenct(request_time, pkt);
+            cpuSidePort.schedTimingResp(pkt, request_time + delay);
         }
     } else {
+        if (pkt->isEviction()) {
+            calculateBusyLatenct(curTick(), pkt);
+        }
+
         DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__,
                 pkt->print());
 
@@ -1534,8 +1545,7 @@ BaseCache::calculateAccessLatency(const CacheBlk* blk, const uint32_t delay,
         // access latency on top of when the block is ready to be accessed.
         const Tick tick = curTick() + delay;
         const Tick when_ready = blk->getWhenReady();
-        if (when_ready > tick &&
-            ticksToCycles(when_ready - tick) > lat) {
+        if (when_ready > tick) {
             lat += ticksToCycles(when_ready - tick);
             DPRINTF(Cache, "block not ready, need %lu cycle\n", ticksToCycles(when_ready - tick));
         }
@@ -1549,6 +1559,25 @@ BaseCache::calculateAccessLatency(const CacheBlk* blk, const uint32_t delay,
     return lat;
 }
 
+Tick
+BaseCache::calculateBusyLatenct(Tick when_ready, PacketPtr pkt)
+{
+    if (sliceNum <= 0) [[likely]] return 0;
+    Addr baddr = pkt->getAddr() >> ceilLog2(blkSize);
+    Addr sliceidx = baddr & (sliceNum - 1);
+    int additional = 1;
+    int opLatency = additional + (lookupLatency == 1 ? 0 : lookupLatency) + (dataLatency == 1 ? 0 : dataLatency);
+    Tick op_lat = cyclesToTicks(Cycles(opLatency));
+    Tick& readytime = sliceReadyTick[sliceidx];
+    if (when_ready >= readytime + op_lat) {
+        readytime = when_ready;
+        return 0;
+    } else {
+        readytime = readytime + op_lat;
+        return readytime + op_lat - when_ready;
+    }
+}
+
 bool
 BaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat,
                   PacketList &writebacks)

src/mem/cache/base.hh

@@ -373,6 +373,8 @@ class BaseCache : public ClockedObject, CacheAccessor
     /** Max Tag read ports for L1 Load/pretche */
     const unsigned tagLoadReadPorts;
 
+    const int sliceNum;
+
     /** Available Tag read ports for L1 Load/pretche */
     unsigned freeTagLoadReadPorts;
 
@@ -431,6 +433,8 @@ class BaseCache : public ClockedObject, CacheAccessor
      */
     std::unique_ptr<Packet> pendingDelete;
 
+    std::vector<Tick> sliceReadyTick;
+
     /**
      * Mark a request as in service (sent downstream in the memory
      * system), effectively making this MSHR the ordering point.
@@ -510,6 +514,8 @@ class BaseCache : public ClockedObject, CacheAccessor
     Cycles calculateAccessLatency(const CacheBlk* blk, const uint32_t delay,
                                   const Cycles lookup_lat) const;
 
+    Tick calculateBusyLatenct(Tick when_ready, PacketPtr pkt);
+
     /**
      * Does all the processing necessary to perform the provided request.
      * @param pkt The memory request to perform.

src/mem/packet_queue.hh

@@ -172,6 +172,9 @@ class PacketQueue : public Drainable
     Tick deferredPacketReadyTime() const
     { return transmitList.empty() ? MaxTick : transmitList.front().tick; }
 
+    Tick lastDeferredPacketReadyTime() const
+    { return transmitList.empty() ? MaxTick : transmitList.back().tick; }
+
     /**
      * Check if a packet corresponding to the same address exists in the
      * queue.

src/mem/qport.hh

@@ -93,6 +93,14 @@ class QueuedResponsePort : public ResponsePort
     void schedTimingResp(PacketPtr pkt, Tick when)
     { respQueue.schedSendTiming(pkt, when); }
 
+    Tick nextReadyTime() {
+      return respQueue.deferredPacketReadyTime();
+    }
+
+    Tick lastReadyTime() {
+      return respQueue.lastDeferredPacketReadyTime();
+    }
+
     /** Check the list of buffered packets against the supplied
      * functional request. */
     bool trySatisfyFunctional(PacketPtr pkt)
@@ -149,6 +157,14 @@ class QueuedRequestPort : public RequestPort
     void schedTimingReq(PacketPtr pkt, Tick when)
     { reqQueue.schedSendTiming(pkt, when); }
 
+    Tick nextReadyTime() {
+      return reqQueue.deferredPacketReadyTime();
+    }
+
+    Tick lastReadyTime() {
+      return reqQueue.lastDeferredPacketReadyTime();
+    }
+
     /**
      * Schedule the sending of a timing snoop response.
      *