cpu-o3: Split operations in the ldst pipeline

Now initiateAcc only does tlb access and is located at s0 of the load/store pipeline.

Load makes cache access and query violations at s1, receives the cache response at s2, and writes back at s3.
Store updates sq and query violations at s1, and writes back at s4.

AMO operations are now executed using `executeAmo`.

Change-Id: Iac678b7de3a690329f279c70fdcd22be4ed22715

src/cpu/o3/iew.cc

@@ -1468,7 +1468,7 @@ IEW::executeInsts()
             // Tell the LDSTQ to execute this instruction (if it is a load).
             if (inst->isAtomic()) {
                 // AMOs are treated like store requests
-                fault = ldstQueue.executeStore(inst);
+                fault = ldstQueue.executeAmo(inst);
 
                 if (inst->isTranslationDelayed() &&
                     fault == NoFault) {

src/cpu/o3/lsq.cc

@@ -43,6 +43,7 @@
 
 #include <algorithm>
 #include <csignal>
+#include <cstdint>
 #include <list>
 #include <string>
 
@@ -51,6 +52,7 @@
 #include "base/trace.hh"
 #include "cpu/o3/cpu.hh"
 #include "cpu/o3/dyn_inst.hh"
+#include "cpu/o3/dyn_inst_ptr.hh"
 #include "cpu/o3/iew.hh"
 #include "cpu/o3/limits.hh"
 #include "debug/Drain.hh"
@@ -319,19 +321,11 @@ LSQ::executePipeSx()
 }
 
 Fault
-LSQ::executeLoad(const DynInstPtr &inst)
+LSQ::executeAmo(const DynInstPtr &inst)
 {
     ThreadID tid = inst->threadNumber;
 
-    return thread[tid].executeLoad(inst);
-}
-
-Fault
-LSQ::executeStore(const DynInstPtr &inst)
-{
-    ThreadID tid = inst->threadNumber;
-
-    return thread[tid].executeStore(inst);
+    return thread[tid].executeAmo(inst);
 }
 
 void
@@ -561,8 +555,12 @@ LSQ::recvFunctionalCustomSignal(PacketPtr pkt, int sig)
     LSQRequest *request = dynamic_cast<LSQRequest*>(pkt->getPrimarySenderState());
     panic_if(!request, "Got packet back with unknown sender state\n");
     if (sig == DcacheRespType::Miss) {
-        // notify cache miss
-        iewStage->loadCancel(request->instruction());
+        if (request->instruction()->isLoad()) {
+            // notify cache miss
+            iewStage->loadCancel(request->instruction());
+            // set cache miss flag in pipeline
+            thread[request->_port.lsqID].setFlagInPipeLine(request->instruction(), LdStFlags::CacheMiss);
+        }
     } else {
         panic("unsupported sig %d in recvFunctionalCustomSignal\n", sig);
     }
@@ -954,6 +952,14 @@ LSQ::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
         request->initiateTranslation();
     }
 
+    if (!isLoad && !isAtomic) {
+        // store inst temporally saves its data in memData
+        inst->memData = new uint8_t[size];
+        memcpy(inst->memData, data, size);
+    }
+
+    inst->effSize = size;
+
     if (!isLoad && !inst->isVector() && size > 1 && addr % size != 0) {
         warn( "Store misaligned: size: %u, Addr: %#lx, code: %d\n", size,
             addr, RiscvISA::ExceptionCode::STORE_ADDR_MISALIGNED);
@@ -963,7 +969,7 @@ LSQ::pushRequest(const DynInstPtr& inst, bool isLoad, uint8_t *data,
     }
 
     /* This is the place were instructions get the effAddr. */
-    if (request->isTranslationComplete()) {
+    if (inst->isAtomic() && request->isTranslationComplete()) {
         if (request->isMemAccessRequired()) {
             inst->effAddr = request->getVaddr();
             inst->effSize = size;

src/cpu/o3/lsq.hh

@@ -76,6 +76,18 @@ class IEW;
 class LSQUnit;
 class StoreBufferEntry;
 
+/** The Flag of Load/Store inst in Pipeline. */
+enum LdStFlags
+{
+    Valid = 0,
+    Replayed,
+    CacheMiss,
+    Squashed,
+    Num_Flags
+};
+
+constexpr uint64_t LdStFlagNum = LdStFlags::Num_Flags;
+
 class LSQ
 {
   public:
@@ -741,11 +753,8 @@ class LSQ
     /** Inserts a store into the LSQ. */
     void insertStore(const DynInstPtr &store_inst);
 
-    /** Executes a load. */
-    Fault executeLoad(const DynInstPtr &inst);
-
-    /** Executes a store. */
-    Fault executeStore(const DynInstPtr &inst);
+    /** Executes an amo inst. */
+    Fault executeAmo(const DynInstPtr &inst);
 
     /** Iq issues a load to load pipeline. */
     void issueToLoadPipe(const DynInstPtr &inst);