cpu-o3: ideal: l2 latency from 16 to 10 cycles, no slice (#249)

Change-Id: I766b593c954d91a600d7b240afa2a308ba0e88d5
OpenXiangShan · Dec 31, 2024 · eaf1c14 · eaf1c14
1 parent d46d2c5
commit eaf1c14
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/configs/example/xiangshan.py b/configs/example/xiangshan.py
@@ -370,6 +370,9 @@ def setKmhV3IdealParams(args, system):
         for i in range(args.num_cpus):
             system.l2_caches[i].size = '2MB'
             system.l2_caches[i].enable_wayprediction = False
+            system.l2_caches[i].slice_num = 0   # 4 -> 0, no slice
+            system.tol2bus_list[i].forward_latency = 0  # 3->0
+            system.tol2bus_list[i].response_latency = 0  # 3->0
 
     if args.l3cache:
         system.l3.enable_wayprediction = False