cpu-o3: non-blocking storebuffer

Change-Id: Id72033c713686fdd631d9217b7385db4b9189811
OpenXiangShan · Oct 12, 2024 · ae149b9 · ae149b9
1 parent 69f3fca
commit ae149b9
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Showing 7 changed files with 306 additions and 199 deletions.
diff --git a/src/cpu/o3/BaseO3CPU.py b/src/cpu/o3/BaseO3CPU.py
@@ -157,8 +157,8 @@ def support_take_over(cls):
     SQEntries = Param.Unsigned(64, "Number of store queue entries")
 
     SbufferEntries = Param.Unsigned(16, "Number of store buffer entries")
-    SbufferEvictThreshold = Param.Unsigned(12, "store buffer eviction threshold")
-    storeBufferInactiveThreshold = Param.Unsigned(100, "store buffer writeback timeout threshold")
+    SbufferEvictThreshold = Param.Unsigned(8, "store buffer eviction threshold")
+    storeBufferInactiveThreshold = Param.Unsigned(800, "store buffer writeback timeout threshold")
 
     LSQDepCheckShift = Param.Unsigned(0,
             "Number of places to shift addr before check")
@@ -191,7 +191,7 @@ def support_take_over(cls):
     numPhysRMiscRegs = Param.Unsigned(40, "Number of physical renameable misc registers")
 
     numDQEntries = Param.Unsigned(18, "Number of entries in the dispQue")
-    numROBEntries = Param.Unsigned(256, "Number of reorder buffer entries")
+    numROBEntries = Param.Unsigned(320, "Number of reorder buffer entries")
 
     smtNumFetchingThreads = Param.Unsigned(1, "SMT Number of Fetching Threads")
     smtFetchPolicy = Param.SMTFetchPolicy('RoundRobin', "SMT Fetch policy")

diff --git a/src/cpu/o3/issue_queue.cc b/src/cpu/o3/issue_queue.cc
@@ -752,7 +752,6 @@ Scheduler::insert(const DynInstPtr& inst)
     auto& iqs = dispTable[inst->opClass()];
     bool inserted = false;
 
-    // std::round
     std::random_shuffle(iqs.begin(), iqs.end());
     for (auto iq : iqs) {
         if (iq->ready()) {

diff --git a/src/cpu/o3/issue_queue.hh b/src/cpu/o3/issue_queue.hh
@@ -138,7 +138,6 @@ class IssueQue : public SimObject
   public:
     inline void clearBusy(uint32_t pi) { portBusy.at(pi) = 0; }
 
-
     IssueQue(const IssueQueParams &params);
     void setIQID(int id) { IQID = id; }
     void setCPU(CPU* cpu);
@@ -147,7 +146,7 @@ class IssueQue : public SimObject
     void tick();
     bool full();
     bool ready();
-    int emptyEntries() const { return instNum; }
+    int emptyEntries() const { return iqsize - instNum; }
     void insert(const DynInstPtr& inst);
     void insertNonSpec(const DynInstPtr& inst);
 

diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc
@@ -1318,8 +1318,8 @@ LSQ::SbufferRequest::recvTimingResp(PacketPtr pkt)
 {
     // Dump inst num, request addr, and packet addr
     DPRINTF(StoreBuffer,
-            "Sbuffer Req::recvTimingResp: entry[%#x] sbuffer index: %lu\n",
-            _packets[0]->getAddr(), this->sbuffer_index);
+            "Sbuffer Req::recvTimingResp: entry[%#x]\n",
+            _packets[0]->getAddr());
     assert(_numOutstandingPackets == 1);
     flags.set(Flag::Complete);
     assert(pkt == _packets.front());
@@ -1485,8 +1485,7 @@ LSQ::SbufferRequest::sendPacketToCache()
 {
     assert(_numOutstandingPackets == 0);
     bool success = _port.sbufferSendPacket(_packets.at(0));
-    DPRINTF(StoreBuffer, "Sbuffer Req::sendPacketToCache: entry[%#x] sbuffer index: %lu\n", _packets[0]->getAddr(),
-            this->sbuffer_index);
+    DPRINTF(StoreBuffer, "Sbuffer Req::sendPacketToCache: entry[%#x]\n", _packets[0]->getAddr());
     if (success) {
         _numOutstandingPackets = 1;
     }

diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh
@@ -74,6 +74,7 @@ namespace o3
 class CPU;
 class IEW;
 class LSQUnit;
+class StoreBufferEntry;
 
 class LSQ
 {
@@ -686,7 +687,7 @@ class LSQ
     {
         CPU* cpu;
       public:
-        uint64_t sbuffer_index=-1;
+        StoreBufferEntry* sbuffer_entry=nullptr;
         SbufferRequest(CPU* cpu, LSQUnit* port, Addr blockpaddr, uint8_t* data);
 
         void addReq(Addr blockVaddr, Addr blockPaddr, const std::vector<bool> byteEnable);