arch-riscv: default disable vs bit, set misa with B-ext, update ref-so #28
Triggered via pull request
August 21, 2024 02:11
Status
Success
Total duration
1h 53m 5s
Artifacts
–
gem5.yml
on: pull_request
XS-GEM5 - Running test checkpoints
1h 25m
XS-GEM5 - Check memory corruption
22m 37s
XS-GEM5 - Test new simulation script on RV64GCB
17m 30s
XS-GEM5 - Test new simulation script on RV64GCBV
15m 9s
XS-GEM5 - Test Multi-core + RV64GCB
27m 14s
Annotations
10 warnings