arch-riscv: default disable vs bit, set misa with B-ext, update ref-so #27
Triggered via pull request
August 20, 2024 08:27
Status
Success
Total duration
2h 7m 14s
Artifacts
–
gem5.yml
on: pull_request
XS-GEM5 - Running test checkpoints
1h 26m
XS-GEM5 - Check memory corruption
22m 44s
XS-GEM5 - Test new simulation script on RV64GCB
17m 18s
XS-GEM5 - Test new simulation script on RV64GCBV
15m 44s
XS-GEM5 - Test Multi-core + RV64GCB
27m 45s
Annotations
10 warnings