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gem5 Test

arch-riscv: default disable vs bit, set misa with B-ext, update ref-so #25

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arch-riscv: default disable vs bit, set misa with B-ext, update ref-so

arch-riscv: default disable vs bit, set misa with B-ext, update ref-so #25

Run time

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Job Run time
XS-GEM5 - Test Multi-core + RV64GCB
7m 26s
XS-GEM5 - Test Multi-core + RV64GCB
6m 57s
XS-GEM5 - Test new simulation script on RV64GCB
17m 30s
XS-GEM5 - Test new simulation script on RV64GCB
8m 13s
XS-GEM5 - Running test checkpoints
15m 25s
XS-GEM5 - Running test checkpoints
7m 21s
XS-GEM5 - Test new simulation script on RV64GCBV
6m 15s
XS-GEM5 - Test new simulation script on RV64GCBV
6m 12s
XS-GEM5 - Check memory corruption
11m 33s
XS-GEM5 - Check memory corruption
1s
1h 26m 53s