RISC-V-pipeline-processor

There are five pipeline stages:

1.Instruction Fetch 2.Instruction Decode 3.Execution 4.Memory 5.Write Back

with hazard detection and forwarding unit

Name		Name	Last commit message	Last commit date
Latest commit History 3 Commits
ALU.v		ALU.v
C_EX_MEM.v		C_EX_MEM.v
C_ID_EX.v		C_ID_EX.v
C_MEM_WB.v		C_MEM_WB.v
Control_path.v		Control_path.v
Data_Memory.v		Data_Memory.v
Data_path.v		Data_path.v
EX_MEM.v		EX_MEM.v
Extend.v		Extend.v
Hazard_detection.v		Hazard_detection.v
ID_EX.v		ID_EX.v
IF_ID.v		IF_ID.v
Instr_Decode.v		Instr_Decode.v
Instruction_Memory.v		Instruction_Memory.v
MEM_WB.v		MEM_WB.v
README.md		README.md
RISC_V_core.v		RISC_V_core.v
Registers.v		Registers.v
Top.v		Top.v
mux2.v		mux2.v
mux3.v		mux3.v

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