535.183.01

CHANGELOG.md

@@ -2,6 +2,8 @@
 
 ## Release 535 Entries
 
+### [535.183.01] 2024-06-04
+
 ### [535.179] 2024-05-09
 
 ### [535.171.04] 2024-03-21

README.md

@@ -1,7 +1,7 @@
 # NVIDIA Linux Open GPU Kernel Module Source
 
 This is the source release of the NVIDIA Linux open GPU kernel modules,
-version 535.179.
+version 535.183.01.
 
 
 ## How to Build
@@ -17,7 +17,7 @@ as root:
 
 Note that the kernel modules built here must be used with GSP
 firmware and user-space NVIDIA GPU driver components from a corresponding
-535.179 driver release.  This can be achieved by installing
+535.183.01 driver release.  This can be achieved by installing
 the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
 option.  E.g.,
 
@@ -180,15 +180,15 @@ software applications.
 ## Compatible GPUs
 
 The open-gpu-kernel-modules can be used on any Turing or later GPU
-(see the table below). However, in the 535.179 release,
+(see the table below). However, in the 535.183.01 release,
 GeForce and Workstation support is still considered alpha-quality.
 
 To enable use of the open kernel modules on GeForce and Workstation GPUs,
 set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module
 parameter to 1. For more details, see the NVIDIA GPU driver end user
 README here:
 
-https://us.download.nvidia.com/XFree86/Linux-x86_64/535.179/README/kernel_open.html
+https://us.download.nvidia.com/XFree86/Linux-x86_64/535.183.01/README/kernel_open.html
 
 In the below table, if three IDs are listed, the first is the PCI Device 
 ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI
@@ -894,6 +894,7 @@ Subsystem Device ID.
 | NVIDIA GeForce RTX 4050 Laptop GPU              | 28A1           |
 | NVIDIA RTX 2000 Ada Generation Laptop GPU       | 28B8           |
 | NVIDIA RTX 1000 Ada Generation Laptop GPU       | 28B9           |
+| NVIDIA RTX 500 Ada Generation Laptop GPU        | 28BA           |
 | NVIDIA RTX 500 Ada Generation Laptop GPU        | 28BB           |
 | NVIDIA GeForce RTX 4060 Laptop GPU              | 28E0           |
 | NVIDIA GeForce RTX 4050 Laptop GPU              | 28E1           |

kernel-open/Kbuild

@@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
 EXTRA_CFLAGS += -I$(src)
 EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
 EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
-EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.179\"
+EXTRA_CFLAGS += -DNV_VERSION_STRING=\"535.183.01\"
 
 ifneq ($(SYSSRCHOST1X),)
  EXTRA_CFLAGS += -I$(SYSSRCHOST1X)

kernel-open/nvidia-uvm/uvm_test.c

@@ -148,24 +148,23 @@ static NV_STATUS uvm_test_verify_bh_affinity(uvm_intr_handler_t *isr, int node)
 static NV_STATUS uvm_test_numa_check_affinity(UVM_TEST_NUMA_CHECK_AFFINITY_PARAMS *params, struct file *filp)
 {
     uvm_gpu_t *gpu;
-    NV_STATUS status;
-    uvm_rm_user_object_t user_rm_va_space = {
-        .rm_control_fd = -1,
-        .user_client = params->client,
-        .user_object = params->smc_part_ref
-    };
+    NV_STATUS status = NV_OK;
 
     if (!UVM_THREAD_AFFINITY_SUPPORTED())
         return NV_ERR_NOT_SUPPORTED;
 
-    status = uvm_gpu_retain_by_uuid(&params->gpu_uuid, &user_rm_va_space, &gpu);
-    if (status != NV_OK)
-        return status;
+    uvm_mutex_lock(&g_uvm_global.global_lock);
+
+    gpu = uvm_gpu_get_by_uuid(&params->gpu_uuid);
+    if (!gpu) {
+        status = NV_ERR_INVALID_DEVICE;
+        goto unlock;
+    }
 
     // If the GPU is not attached to a NUMA node, there is nothing to do.
     if (gpu->parent->closest_cpu_numa_node == NUMA_NO_NODE) {
         status = NV_ERR_NOT_SUPPORTED;
-        goto release;
+        goto unlock;
     }
 
     if (gpu->parent->replayable_faults_supported) {
@@ -174,15 +173,15 @@ static NV_STATUS uvm_test_numa_check_affinity(UVM_TEST_NUMA_CHECK_AFFINITY_PARAM
                                               gpu->parent->closest_cpu_numa_node);
         uvm_gpu_replayable_faults_isr_unlock(gpu->parent);
         if (status != NV_OK)
-            goto release;
+            goto unlock;
 
         if (gpu->parent->non_replayable_faults_supported) {
             uvm_gpu_non_replayable_faults_isr_lock(gpu->parent);
             status = uvm_test_verify_bh_affinity(&gpu->parent->isr.non_replayable_faults,
                                                   gpu->parent->closest_cpu_numa_node);
             uvm_gpu_non_replayable_faults_isr_unlock(gpu->parent);
             if (status != NV_OK)
-                goto release;
+                goto unlock;
         }
 
         if (gpu->parent->access_counters_supported) {
@@ -192,8 +191,9 @@ static NV_STATUS uvm_test_numa_check_affinity(UVM_TEST_NUMA_CHECK_AFFINITY_PARAM
             uvm_gpu_access_counters_isr_unlock(gpu->parent);
         }
     }
-release:
-    uvm_gpu_release(gpu);
+
+unlock:
+    uvm_mutex_unlock(&g_uvm_global.global_lock);
     return status;
 }
 

kernel-open/nvidia-uvm/uvm_test_ioctl.h

@@ -1203,8 +1203,6 @@ typedef struct
 typedef struct
 {
     NvProcessorUuid                 gpu_uuid;                                           // In
-    NvHandle                        client;                                             // In
-    NvHandle                        smc_part_ref;                                       // In
 
     NV_STATUS                       rmStatus;                                           // Out
 } UVM_TEST_NUMA_CHECK_AFFINITY_PARAMS;

src/common/displayport/inc/dp_connectorimpl.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -299,6 +299,7 @@ namespace DisplayPort
         bool        bDisableSSC;
         bool        bEnableFastLT;
         NvU32       maxLinkRateFromRegkey;
+        bool        bFlushTimeslotWhenDirty;
 
         //
         // Latency(ms) to apply between link-train and FEC enable for bug

src/common/displayport/inc/dp_regkeydatabase.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -66,7 +66,7 @@
 #define NV_DP_REGKEY_POWER_DOWN_PHY                   "DP_POWER_DOWN_PHY"
 
 //
-// Regkey to re-assess max link if the first assessed link config 
+// Regkey to re-assess max link if the first assessed link config
 // is lower than the panel max
 //
 #define NV_DP_REGKEY_REASSESS_MAX_LINK                "DP_REASSESS_MAX_LINK"
@@ -77,11 +77,12 @@
 //
 #define NV_DP_DSC_MST_CAP_BUG_3143315                  "DP_DSC_MST_CAP_BUG_3143315"
 
-//
 // Bug 4388987 : This regkey will disable reading PCON caps for MST.
-//
 #define NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED       "DP_BUG_4388987_WAR"
 
+// Bug 4426624: Flush timeslot change to HW when dirty bit is set.
+#define NV_DP_REGKEY_FLUSH_TIMESLOT_INFO_WHEN_DIRTY    "DP_BUG_4426624_WAR"
+
 //
 // Data Base used to store all the regkey values.
 // The actual data base is declared statically in dp_evoadapter.cpp.
@@ -117,6 +118,7 @@ struct DP_REGKEY_DATABASE
     bool  bCheckFECForDynamicMuxDSCPanel;
     bool  bReassessMaxLink;
     bool  bMSTPCONCapsReadDisabled;
+    bool  bFlushTimeslotWhenDirty;
 };
 
 #endif //INCLUDED_DP_REGKEYDATABASE_H

src/common/displayport/src/dp_connectorimpl.cpp

@@ -172,6 +172,7 @@ void ConnectorImpl::applyRegkeyOverrides(const DP_REGKEY_DATABASE& dpRegkeyDatab
     this->bDscMstCapBug3143315          = dpRegkeyDatabase.bDscMstCapBug3143315;
     this->bPowerDownPhyBeforeD3         = dpRegkeyDatabase.bPowerDownPhyBeforeD3;
     this->bReassessMaxLink              = dpRegkeyDatabase.bReassessMaxLink;
+    this->bFlushTimeslotWhenDirty       = dpRegkeyDatabase.bFlushTimeslotWhenDirty;
 }
 
 void ConnectorImpl::setPolicyModesetOrderMitigation(bool enabled)
@@ -5234,7 +5235,8 @@ void ConnectorImpl::beforeDeleteStream(GroupImpl * group, bool forFlushMode)
         }
     }
 
-    if (linkUseMultistream() && group && group->isHeadAttached() && group->timeslot.count)
+    if (linkUseMultistream() && group && group->isHeadAttached() &&
+        (group->timeslot.count || (this->bFlushTimeslotWhenDirty && group->timeslot.hardwareDirty)))
     {
         // Detach all the panels from payload
         for (Device * d = group->enumDevices(0); d; d = group->enumDevices(d))

src/common/displayport/src/dp_evoadapter.cpp

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 1993-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -96,7 +96,8 @@ const struct
     {NV_DP_CHECK_FEC_FOR_DDS_DSC_PANEL,             &dpRegkeyDatabase.bCheckFECForDynamicMuxDSCPanel,  DP_REG_VAL_BOOL},
     {NV_DP_REGKEY_POWER_DOWN_PHY,                   &dpRegkeyDatabase.bPowerDownPhyBeforeD3,           DP_REG_VAL_BOOL},
     {NV_DP_REGKEY_REASSESS_MAX_LINK,                &dpRegkeyDatabase.bReassessMaxLink,                DP_REG_VAL_BOOL},
-    {NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED,      &dpRegkeyDatabase.bMSTPCONCapsReadDisabled,        DP_REG_VAL_BOOL}
+    {NV_DP_REGKEY_MST_PCON_CAPS_READ_DISABLED,      &dpRegkeyDatabase.bMSTPCONCapsReadDisabled,        DP_REG_VAL_BOOL},
+    {NV_DP_REGKEY_FLUSH_TIMESLOT_INFO_WHEN_DIRTY,   &dpRegkeyDatabase.bFlushTimeslotWhenDirty,         DP_REG_VAL_BOOL}
 };
 
 EvoMainLink::EvoMainLink(EvoInterface * provider, Timer * timer) :

src/common/inc/nvBldVer.h

@@ -36,25 +36,25 @@
 // and then checked back in. You cannot make changes to these sections without
 // corresponding changes to the buildmeister script
 #ifndef NV_BUILD_BRANCH
-    #define NV_BUILD_BRANCH             r535_00
+    #define NV_BUILD_BRANCH             r538_67
 #endif
 #ifndef NV_PUBLIC_BRANCH
-    #define NV_PUBLIC_BRANCH             r535_00
+    #define NV_PUBLIC_BRANCH             r538_67
 #endif
 
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
-#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r535/r535_00-537"
-#define NV_BUILD_CHANGELIST_NUM         (34218726)
+#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r535/r538_67-552"
+#define NV_BUILD_CHANGELIST_NUM         (34280977)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "rel/gpu_drv/r535/r535_00-537"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34218726)
+#define NV_BUILD_NAME                   "rel/gpu_drv/r535/r538_67-552"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34280977)
 
 #else     /* Windows builds */
-#define NV_BUILD_BRANCH_VERSION         "r535_00-549"
-#define NV_BUILD_CHANGELIST_NUM         (34218726)
+#define NV_BUILD_BRANCH_VERSION         "r538_67-1"
+#define NV_BUILD_CHANGELIST_NUM         (34280977)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "538.62"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34218726)
+#define NV_BUILD_NAME                   "538.69"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (34280977)
 #define NV_BUILD_BRANCH_BASE_VERSION    R535
 #endif
 // End buildmeister python edited section

src/common/inc/nvUnixVersion.h

@@ -4,7 +4,7 @@
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
     (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
 
-#define NV_VERSION_STRING               "535.179"
+#define NV_VERSION_STRING               "535.183.01"
 
 #else
 

src/common/inc/swref/published/ampere/ga100/dev_runlist.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2003-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2003-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -24,4 +24,64 @@
 #ifndef __ga100_dev_runlist_h__
 #define __ga100_dev_runlist_h__
 #define NV_CHRAM_CHANNEL(i)                            (0x000+(i)*4) /* RW-4A */
+#define NV_CHRAM_CHANNEL__SIZE_1   2048 /*       */
+#define NV_CHRAM_CHANNEL_WRITE_CONTROL                          0:0 /* -WIVF */
+#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_SET_BITS     0x00000000 /* -WI-V */
+#define NV_CHRAM_CHANNEL_WRITE_CONTROL_ONES_CLEAR_BITS   0x00000001 /* -W--V */
+#define NV_CHRAM_CHANNEL_ENABLE                                 1:1 /* RWIVF */
+#define NV_CHRAM_CHANNEL_ENABLE_NOT_IN_USE               0x00000000 /* RWI-V */
+#define NV_CHRAM_CHANNEL_ENABLE_IN_USE                   0x00000001 /* RW--V */
+#define NV_CHRAM_CHANNEL_NEXT                                   2:2 /* RWIVF */
+#define NV_CHRAM_CHANNEL_NEXT_FALSE                      0x00000000 /* RWI-V */
+#define NV_CHRAM_CHANNEL_NEXT_TRUE                       0x00000001 /* RW--V */
+#define NV_CHRAM_CHANNEL_BUSY                                   3:3 /* R-IVF */
+#define NV_CHRAM_CHANNEL_BUSY_FALSE                      0x00000000 /* R-I-V */
+#define NV_CHRAM_CHANNEL_BUSY_TRUE                       0x00000001 /* R---V */
+#define NV_CHRAM_CHANNEL_PBDMA_FAULTED                          4:4 /* RWIVF */
+#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_FALSE             0x00000000 /* RWI-V */
+#define NV_CHRAM_CHANNEL_PBDMA_FAULTED_TRUE              0x00000001 /* RW--V */
+#define NV_CHRAM_CHANNEL_ENG_FAULTED                            5:5 /* RWIVF */
+#define NV_CHRAM_CHANNEL_ENG_FAULTED_FALSE               0x00000000 /* RWI-V */
+#define NV_CHRAM_CHANNEL_ENG_FAULTED_TRUE                0x00000001 /* RW--V */
+#define NV_CHRAM_CHANNEL_ON_PBDMA                               6:6 /* R-IVF */
+#define NV_CHRAM_CHANNEL_ON_PBDMA_FALSE                  0x00000000 /* R-I-V */
+#define NV_CHRAM_CHANNEL_ON_PBDMA_TRUE                   0x00000001 /* R---V */
+#define NV_CHRAM_CHANNEL_ON_ENG                                 7:7 /* R-IVF */
+#define NV_CHRAM_CHANNEL_ON_ENG_FALSE                    0x00000000 /* R-I-V */
+#define NV_CHRAM_CHANNEL_ON_ENG_TRUE                     0x00000001 /* R---V */
+#define NV_CHRAM_CHANNEL_PENDING                                8:8 /* RWIVF */
+#define NV_CHRAM_CHANNEL_PENDING_FALSE                   0x00000000 /* RWI-V */
+#define NV_CHRAM_CHANNEL_PENDING_TRUE                    0x00000001 /* RW--V */
+#define NV_CHRAM_CHANNEL_CTX_RELOAD                             9:9 /* RWIVF */
+#define NV_CHRAM_CHANNEL_CTX_RELOAD_FALSE                0x00000000 /* RWI-V */
+#define NV_CHRAM_CHANNEL_CTX_RELOAD_TRUE                 0x00000001 /* RW--V */
+#define NV_CHRAM_CHANNEL_PBDMA_BUSY                           10:10 /* R-IVF */
+#define NV_CHRAM_CHANNEL_PBDMA_BUSY_FALSE                0x00000000 /* R-I-V */
+#define NV_CHRAM_CHANNEL_PBDMA_BUSY_TRUE                 0x00000001 /* R---V */
+#define NV_CHRAM_CHANNEL_ENG_BUSY                             11:11 /* R-IVF */
+#define NV_CHRAM_CHANNEL_ENG_BUSY_FALSE                  0x00000000 /* R-I-V */
+#define NV_CHRAM_CHANNEL_ENG_BUSY_TRUE                   0x00000001 /* R---V */
+#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL                         12:12 /* RWIVF */
+#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_FALSE              0x00000000 /* RWI-V */
+#define NV_CHRAM_CHANNEL_ACQUIRE_FAIL_TRUE               0x00000001 /* RW--V */
+#define NV_CHRAM_CHANNEL_UPDATE                                31:0 /*       */
+#define NV_CHRAM_CHANNEL_UPDATE_ENABLE_CHANNEL           0x00000002 /*       */
+#define NV_CHRAM_CHANNEL_UPDATE_DISABLE_CHANNEL          0x00000003 /*       */
+#define NV_CHRAM_CHANNEL_UPDATE_FORCE_CTX_RELOAD         0x00000200 /*       */
+#define NV_CHRAM_CHANNEL_UPDATE_RESET_PBDMA_FAULTED      0x00000011 /*       */
+#define NV_CHRAM_CHANNEL_UPDATE_RESET_ENG_FAULTED        0x00000021 /*       */
+#define NV_CHRAM_CHANNEL_UPDATE_CLEAR_CHANNEL            0xFFFFFFFF /*       */
+#define NV_RUNLIST_PREEMPT                                     0x098 /* RW-4R */
+#define NV_RUNLIST_PREEMPT_ID                                    11:0 /*       */
+#define NV_RUNLIST_PREEMPT_ID_HW                   10:0 /* RWIUF */
+#define NV_RUNLIST_PREEMPT_ID_HW_NULL                      0x00000000 /* RWI-V */
+#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING                  20:20 /* R-IVF */
+#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_FALSE       0x00000000 /* R-I-V */
+#define NV_RUNLIST_PREEMPT_TSG_PREEMPT_PENDING_TRUE        0x00000001 /* R---V */
+#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING              21:21 /* R-IVF */
+#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_FALSE   0x00000000 /* R-I-V */
+#define NV_RUNLIST_PREEMPT_RUNLIST_PREEMPT_PENDING_TRUE    0x00000001 /* R---V */
+#define NV_RUNLIST_PREEMPT_TYPE                                 25:24 /* RWIVF */
+#define NV_RUNLIST_PREEMPT_TYPE_RUNLIST                    0x00000000 /* RWI-V */
+#define NV_RUNLIST_PREEMPT_TYPE_TSG                        0x00000001 /* RW--V */
 #endif // __ga100_dev_runlist_h__

src/common/nvlink/interface/nvlink.h

@@ -70,8 +70,8 @@ extern "C" {
 
 // Link Transition Timeouts in miliseconds
 #define NVLINK_TRANSITION_OFF_TIMEOUT        1
-#define NVLINK_TRANSITION_SAFE_TIMEOUT       300
-#define NVLINK_TRANSITION_HS_TIMEOUT         8000
+#define NVLINK_TRANSITION_SAFE_TIMEOUT       70
+#define NVLINK_TRANSITION_HS_TIMEOUT         7000
 #define NVLINK_TRANSITION_ACTIVE_PENDING     2000
 #define NVLINK_TRANSITION_POST_HS_TIMEOUT    70