550.142

README.md

@@ -1,7 +1,7 @@
 # NVIDIA Linux Open GPU Kernel Module Source
 
 This is the source release of the NVIDIA Linux open GPU kernel modules,
-version 550.135.
+version 550.142.
 
 
 ## How to Build
@@ -17,7 +17,7 @@ as root:
 
 Note that the kernel modules built here must be used with GSP
 firmware and user-space NVIDIA GPU driver components from a corresponding
-550.135 driver release.  This can be achieved by installing
+550.142 driver release.  This can be achieved by installing
 the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
 option.  E.g.,
 
@@ -188,7 +188,7 @@ encountered specific to them.
 For details on feature support and limitations, see the NVIDIA GPU driver
 end user README here:
 
-https://us.download.nvidia.com/XFree86/Linux-x86_64/550.135/README/kernel_open.html
+https://us.download.nvidia.com/XFree86/Linux-x86_64/550.142/README/kernel_open.html
 
 For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
 Package for more details.
@@ -755,7 +755,6 @@ Subsystem Device ID.
 | NVIDIA H20                                      | 2329 10DE 198B |
 | NVIDIA H20                                      | 2329 10DE 198C |
 | NVIDIA H20-3e                                   | 232C 10DE 2063 |
-| NVIDIA H20-3e                                   | 232C 10DE 2064 |
 | NVIDIA H100 80GB HBM3                           | 2330 10DE 16C0 |
 | NVIDIA H100 80GB HBM3                           | 2330 10DE 16C1 |
 | NVIDIA H100 PCIe                                | 2331 10DE 1626 |
@@ -920,6 +919,7 @@ Subsystem Device ID.
 | NVIDIA GeForce RTX 4060                         | 2882           |
 | NVIDIA GeForce RTX 4060 Laptop GPU              | 28A0           |
 | NVIDIA GeForce RTX 4050 Laptop GPU              | 28A1           |
+| NVIDIA GeForce RTX 3050 A Laptop GPU            | 28A3           |
 | NVIDIA RTX 2000 Ada Generation                  | 28B0 1028 1870 |
 | NVIDIA RTX 2000 Ada Generation                  | 28B0 103C 1870 |
 | NVIDIA RTX 2000E Ada Generation                 | 28B0 103C 1871 |

kernel-open/Kbuild

@@ -57,6 +57,20 @@ ifeq ($(NV_UNDEF_BEHAVIOR_SANITIZER),1)
  UBSAN_SANITIZE := y
 endif
 
+#
+# Command to create a symbolic link, explicitly resolving the symlink target
+# to an absolute path to abstract away the difference between Linux < 6.13,
+# where the CWD is the Linux kernel source tree for Kbuild extmod builds, and
+# Linux >= 6.13, where the CWD is the external module source tree.
+#
+# This is used to create the nv*-kernel.o -> nv*-kernel.o_binary symlinks for
+# kernel modules which use precompiled binary object files.
+#
+
+quiet_cmd_symlink = SYMLINK $@
+ cmd_symlink = ln -sf $(abspath $<) $@
+
+
 $(foreach _module, $(NV_KERNEL_MODULES), \
  $(eval include $(src)/$(_module)/$(_module).Kbuild))
 
@@ -72,7 +86,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
 EXTRA_CFLAGS += -I$(src)
 EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
 EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
-EXTRA_CFLAGS += -DNV_VERSION_STRING=\"550.135\"
+EXTRA_CFLAGS += -DNV_VERSION_STRING=\"550.142\"
 
 ifneq ($(SYSSRCHOST1X),)
  EXTRA_CFLAGS += -I$(SYSSRCHOST1X)

kernel-open/nvidia-modeset/nvidia-modeset.Kbuild

@@ -40,9 +40,6 @@ NV_KERNEL_MODULE_TARGETS += $(NVIDIA_MODESET_KO)
 NVIDIA_MODESET_BINARY_OBJECT := $(src)/nvidia-modeset/nv-modeset-kernel.o_binary
 NVIDIA_MODESET_BINARY_OBJECT_O := nvidia-modeset/nv-modeset-kernel.o
 
-quiet_cmd_symlink = SYMLINK $@
-cmd_symlink = ln -sf $< $@
-
 targets += $(NVIDIA_MODESET_BINARY_OBJECT_O)
 
 $(obj)/$(NVIDIA_MODESET_BINARY_OBJECT_O): $(NVIDIA_MODESET_BINARY_OBJECT) FORCE

kernel-open/nvidia-uvm/uvm.c

@@ -682,6 +682,9 @@ static void uvm_vm_open_semaphore_pool(struct vm_area_struct *vma)
     // Semaphore pool vmas do not have vma wrappers, but some functions will
     // assume vm_private_data is a wrapper.
     vma->vm_private_data = NULL;
+#if defined(VM_WIPEONFORK)
+    nv_vm_flags_set(vma, VM_WIPEONFORK);
+#endif
 
     if (is_fork) {
         // If we forked, leave the parent vma alone.

kernel-open/nvidia/nvidia.Kbuild

@@ -40,9 +40,6 @@ NVIDIA_KO = nvidia/nvidia.ko
 NVIDIA_BINARY_OBJECT := $(src)/nvidia/nv-kernel.o_binary
 NVIDIA_BINARY_OBJECT_O := nvidia/nv-kernel.o
 
-quiet_cmd_symlink = SYMLINK $@
- cmd_symlink = ln -sf $< $@
-
 targets += $(NVIDIA_BINARY_OBJECT_O)
 
 $(obj)/$(NVIDIA_BINARY_OBJECT_O): $(NVIDIA_BINARY_OBJECT) FORCE

src/common/inc/nvBldVer.h

@@ -43,18 +43,18 @@
 #endif
 
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS)
-#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r550/r550_00-475"
-#define NV_BUILD_CHANGELIST_NUM         (35120799)
+#define NV_BUILD_BRANCH_VERSION         "rel/gpu_drv/r550/r550_00-505"
+#define NV_BUILD_CHANGELIST_NUM         (35247928)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "rel/gpu_drv/r550/r550_00-475"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35120799)
+#define NV_BUILD_NAME                   "rel/gpu_drv/r550/r550_00-505"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35247928)
 
 #else     /* Windows builds */
-#define NV_BUILD_BRANCH_VERSION         "r550_00-438"
-#define NV_BUILD_CHANGELIST_NUM         (35120799)
+#define NV_BUILD_BRANCH_VERSION         "r550_00-470"
+#define NV_BUILD_CHANGELIST_NUM         (35247928)
 #define NV_BUILD_TYPE                   "Official"
-#define NV_BUILD_NAME                   "553.35"
-#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35120799)
+#define NV_BUILD_NAME                   "553.50"
+#define NV_LAST_OFFICIAL_CHANGELIST_NUM (35247928)
 #define NV_BUILD_BRANCH_BASE_VERSION    R550
 #endif
 // End buildmeister python edited section

src/common/inc/nvUnixVersion.h

@@ -4,7 +4,7 @@
 #if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
     (defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
 
-#define NV_VERSION_STRING               "550.135"
+#define NV_VERSION_STRING               "550.142"
 
 #else
 

src/common/inc/nvlog_defs.h

@@ -102,9 +102,10 @@ struct _NVLOG_BUFFER
 
 #define NVLOG_MAX_BUFFERS_v11       16
 #define NVLOG_MAX_BUFFERS_v12       256
+#define NVLOG_MAX_BUFFERS_v13       3840
 
-#define NVLOG_MAX_BUFFERS           NVLOG_MAX_BUFFERS_v12
-#define NVLOG_LOGGER_VERSION        12          // v1.2
+#define NVLOG_MAX_BUFFERS           NVLOG_MAX_BUFFERS_v13
+#define NVLOG_LOGGER_VERSION        13          // v1.3
 
 // Due to this file's peculiar location, NvPort may or may not be includable
 typedef struct PORT_SPINLOCK PORT_SPINLOCK;

src/common/nvswitch/kernel/smbpbi_nvswitch.c

@@ -89,10 +89,10 @@ nvswitch_smbpbi_post_init
 
     if (status == NVL_SUCCESS)
     {
-#if defined(DEBUG) || defined(DEVELOP) || defined(NV_MODS)
+#if defined(DEBUG) || defined(DEVELOP)
         nvswitch_lib_smbpbi_log_sxid(device, NVSWITCH_ERR_NO_ERROR,
                                      "NVSWITCH SMBPBI server is online.");
-#endif // defined(DEBUG) || defined(DEVELOP) || defined(NV_MODS)
+#endif // defined(DEBUG) || defined(DEVELOP)
 
         NVSWITCH_PRINT(device, INFO, "%s: SMBPBI POST INIT completed\n", __FUNCTION__);
     }

src/common/sdk/nvidia/inc/ctrl/ctrl0000/ctrl0000nvd.h

@@ -256,7 +256,7 @@ typedef struct NV0000_CTRL_NVD_GET_TIMESTAMP_PARAMS {
 #define NV0000_CTRL_NVD_SIGNATURE_SIZE     (4)
 
 /* Maximum number of buffers */
-#define NV0000_CTRL_NVD_MAX_BUFFERS        (256)
+#define NV0000_CTRL_NVD_MAX_BUFFERS        (3840)
 
 #define NV0000_CTRL_NVD_GET_NVLOG_INFO_PARAMS_MESSAGE_ID (0x4U)
 

src/common/sdk/nvidia/inc/ctrl/ctrl0080/ctrl0080internal.h

@@ -114,4 +114,16 @@ typedef struct NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PAR
     NvHandle clientHandles[NV_FIFO_PERMANENTLY_DISABLE_CHANNELS_MAX_CLIENTS];
 } NV0080_CTRL_INTERNAL_FIFO_RC_AND_PERMANENTLY_DISABLE_CHANNELS_PARAMS;
 
-/* ctrl0080internal_h */
+
+
+#define NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x45U)
+
+typedef struct NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS {
+    NvBool bTeardown;
+} NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS;
+
+#define NV0080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x802046) /* finn: Evaluated from "(FINN_NV01_DEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */
+#define NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x46U)
+
+typedef NV0080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS;
+

src/common/sdk/nvidia/inc/ctrl/ctrl2080/ctrl2080internal.h

@@ -863,19 +863,6 @@ typedef NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS NV2080
 
 #define NV2080_CTRL_CMD_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE (0x20800a43) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_MIGMGR_PROMOTE_GPU_INSTANCE_MEM_RANGE_PARAMS_MESSAGE_ID" */
 
-
-
-#define NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x45U)
-
-typedef struct NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS {
-    NvBool bTeardown;
-} NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS;
-
-#define NV2080_CTRL_CMD_INTERNAL_KGR_INIT_BUG4208224_WAR (0x20800a46) /* finn: Evaluated from "(FINN_NV20_SUBDEVICE_0_INTERNAL_INTERFACE_ID << 8) | NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID" */
-#define NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS_MESSAGE_ID (0x46U)
-
-typedef NV2080_CTRL_INTERNAL_GR_INIT_BUG4208224_WAR_PARAMS NV2080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS;
-
 typedef struct NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES {
     NvBool bPerSubCtxheaderSupported;
 } NV2080_CTRL_INTERNAL_STATIC_GR_PDB_PROPERTIES;

src/common/uproc/os/common/include/liblogdecode.h

@@ -42,7 +42,7 @@ extern "C" {
 #    define LIBOS_LOG_DECODE_ENABLE 1
 #    define LIBOS_LOG_TO_NVLOG      0
 
-#    define LIBOS_LOG_MAX_LOGS    160   // Max logs for all GPUs for offline decoder
+#    define LIBOS_LOG_MAX_LOGS    3840   // Max logs for all GPUs for offline decoder
 
 #else
 #    error "Need to define either NVRM or LIBOS_LOG_OFFLINE_DECODER."

src/nvidia/arch/nvalloc/common/inc/nvcst.h

@@ -66,6 +66,7 @@ CHIPSET_SETUP_FUNC(Intel_4381_setupFunc)
 CHIPSET_SETUP_FUNC(Intel_7A82_setupFunc)
 CHIPSET_SETUP_FUNC(Intel_7A04_setupFunc)
 CHIPSET_SETUP_FUNC(Intel_5795_setupFunc)
+CHIPSET_SETUP_FUNC(Intel_1B81_setupFunc)
 CHIPSET_SETUP_FUNC(SiS_656_setupFunc)
 CHIPSET_SETUP_FUNC(ATI_RS400_setupFunc)
 CHIPSET_SETUP_FUNC(ATI_RS480_setupFunc)
@@ -189,8 +190,8 @@ CSINFO chipsetInfo[] =
     {PCI_VENDOR_ID_INTEL,       0x4385, CS_INTEL_4381,      "Intel-RocketLake",     Intel_4381_setupFunc},
     {PCI_VENDOR_ID_INTEL,       0x7A82, CS_INTEL_7A82,      "Intel-AlderLake",      Intel_7A82_setupFunc},
     {PCI_VENDOR_ID_INTEL,       0x7A84, CS_INTEL_7A82,      "Intel-AlderLake",      Intel_7A82_setupFunc},
-    {PCI_VENDOR_ID_INTEL,       0x1B81, CS_INTEL_1B81,      "Intel-SapphireRapids", NULL},
-    {PCI_VENDOR_ID_INTEL,       0x7A8A, CS_INTEL_1B81,      "Intel-SapphireRapids", NULL},
+    {PCI_VENDOR_ID_INTEL,       0x1B81, CS_INTEL_1B81,      "Intel-SapphireRapids", Intel_1B81_setupFunc},
+    {PCI_VENDOR_ID_INTEL,       0x7A8A, CS_INTEL_1B81,      "Intel-SapphireRapids", Intel_1B81_setupFunc},
     {PCI_VENDOR_ID_INTEL,       0x18DC, CS_INTEL_18DC,      "Intel-IceLake",        NULL},
     {PCI_VENDOR_ID_INTEL,       0x7A04, CS_INTEL_7A04,      "Intel-RaptorLake",     Intel_7A04_setupFunc},
     {PCI_VENDOR_ID_INTEL,       0x5795, CS_INTEL_5795,      "Intel-GraniteRapids",  Intel_5795_setupFunc},

src/nvidia/arch/nvalloc/common/inc/nvpcie.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2000-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2000-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -211,18 +211,21 @@
 // to any specific hardware.
 //
 //
-#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0                       0x000000C8
-#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_ID                           7:0
-#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_NEXT                        15:8
-#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_LENGTH                     23:16
-#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_SIG_LO                     31:24
-#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1                       0x000000CC
-#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_SIG_HI                      15:0
-#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_VERSION                    18:16
-#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_PEER_CLIQUE_ID             22:19
-#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RSVD                       31:23
-
-#define NV_PCI_VIRTUAL_P2P_APPROVAL_SIGNATURE                   0x00503250
+#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0                            0x000000C8
+#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_ID                                7:0
+#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_NEXT                             15:8
+#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_LENGTH                          23:16
+#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_0_SIG_LO                          31:24
+#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1                            0x000000CC
+#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_SIG_HI                           15:0
+#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_VERSION                         18:16
+#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_PEER_CLIQUE_ID                  22:19
+#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RELAXED_ORDERING                23:23
+#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RELAXED_ORDERING_DEFAULT   0x00000000
+#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RELAXED_ORDERING_DISABLE   0x00000001
+#define NV_PCI_VIRTUAL_P2P_APPROVAL_CAP_1_RSVD                            31:24
+
+#define NV_PCI_VIRTUAL_P2P_APPROVAL_SIGNATURE                        0x00503250
 
 // Chipset-specific definitions.
 // Intel SantaRosa definitions

src/nvidia/generated/g_device_nvoc.c

@@ -1142,14 +1142,29 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_Device[]
         /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo),
 #if NV_PRINTF_STRINGS_ALLOWED
         /*func=*/       "deviceCtrlCmdInternalPerfCudaLimitSetControl"
+#endif
+    },
+    {               /*  [63] */
+#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u)
+        /*pFunc=*/      (void (*)(void)) NULL,
+#else
+        /*pFunc=*/      (void (*)(void)) deviceCtrlCmdKGrInternalInitBug4208224War_IMPL,
+#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u)
+        /*flags=*/      0xe40u,
+        /*accessRight=*/0x0u,
+        /*methodId=*/   0x802046u,
+        /*paramSize=*/  sizeof(NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS),
+        /*pClassInfo=*/ &(__nvoc_class_def_Device.classInfo),
+#if NV_PRINTF_STRINGS_ALLOWED
+        /*func=*/       "deviceCtrlCmdKGrInternalInitBug4208224War"
 #endif
     },
 
 };
 
 const struct NVOC_EXPORT_INFO __nvoc_export_info_Device = 
 {
-    /*numEntries=*/     63,
+    /*numEntries=*/     64,
     /*pExportEntries=*/ __nvoc_exported_method_def_Device
 };
 
@@ -1298,6 +1313,10 @@ static void __nvoc_init_funcTable_Device_1(Device *pThis, RmHalspecOwner *pRmhal
     pThis->__deviceCtrlCmdKGrSetTpcPartitionMode__ = &deviceCtrlCmdKGrSetTpcPartitionMode_IMPL;
 #endif
 
+#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xe40u)
+    pThis->__deviceCtrlCmdKGrInternalInitBug4208224War__ = &deviceCtrlCmdKGrInternalInitBug4208224War_IMPL;
+#endif
+
 #if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x210u)
     pThis->__deviceCtrlCmdFbGetCompbitStoreInfo__ = &deviceCtrlCmdFbGetCompbitStoreInfo_IMPL;
 #endif

src/nvidia/generated/g_device_nvoc.h

@@ -112,6 +112,7 @@ struct Device {
     NV_STATUS (*__deviceCtrlCmdKGrGetInfoV2__)(struct Device *, NV0080_CTRL_GR_GET_INFO_V2_PARAMS *);
     NV_STATUS (*__deviceCtrlCmdKGrGetTpcPartitionMode__)(struct Device *, NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *);
     NV_STATUS (*__deviceCtrlCmdKGrSetTpcPartitionMode__)(struct Device *, NV0080_CTRL_GR_TPC_PARTITION_MODE_PARAMS *);
+    NV_STATUS (*__deviceCtrlCmdKGrInternalInitBug4208224War__)(struct Device *, NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS *);
     NV_STATUS (*__deviceCtrlCmdFbGetCompbitStoreInfo__)(struct Device *, NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS *);
     NV_STATUS (*__deviceCtrlCmdFbGetCaps__)(struct Device *, NV0080_CTRL_FB_GET_CAPS_PARAMS *);
     NV_STATUS (*__deviceCtrlCmdFbGetCapsV2__)(struct Device *, NV0080_CTRL_FB_GET_CAPS_V2_PARAMS *);
@@ -250,6 +251,7 @@ NV_STATUS __nvoc_objCreate_Device(Device**, Dynamic*, NvU32, struct CALL_CONTEXT
 #define deviceCtrlCmdKGrGetInfoV2(pDevice, pParams) deviceCtrlCmdKGrGetInfoV2_DISPATCH(pDevice, pParams)
 #define deviceCtrlCmdKGrGetTpcPartitionMode(pDevice, pParams) deviceCtrlCmdKGrGetTpcPartitionMode_DISPATCH(pDevice, pParams)
 #define deviceCtrlCmdKGrSetTpcPartitionMode(pDevice, pParams) deviceCtrlCmdKGrSetTpcPartitionMode_DISPATCH(pDevice, pParams)
+#define deviceCtrlCmdKGrInternalInitBug4208224War(pDevice, pParams) deviceCtrlCmdKGrInternalInitBug4208224War_DISPATCH(pDevice, pParams)
 #define deviceCtrlCmdFbGetCompbitStoreInfo(pDevice, pCompbitStoreParams) deviceCtrlCmdFbGetCompbitStoreInfo_DISPATCH(pDevice, pCompbitStoreParams)
 #define deviceCtrlCmdFbGetCaps(pDevice, pFbCapsParams) deviceCtrlCmdFbGetCaps_DISPATCH(pDevice, pFbCapsParams)
 #define deviceCtrlCmdFbGetCapsV2(pDevice, pFbCapsParams) deviceCtrlCmdFbGetCapsV2_DISPATCH(pDevice, pFbCapsParams)
@@ -470,6 +472,12 @@ static inline NV_STATUS deviceCtrlCmdKGrSetTpcPartitionMode_DISPATCH(struct Devi
     return pDevice->__deviceCtrlCmdKGrSetTpcPartitionMode__(pDevice, pParams);
 }
 
+NV_STATUS deviceCtrlCmdKGrInternalInitBug4208224War_IMPL(struct Device *pDevice, NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS *pParams);
+
+static inline NV_STATUS deviceCtrlCmdKGrInternalInitBug4208224War_DISPATCH(struct Device *pDevice, NV0080_CTRL_INTERNAL_KGR_INIT_BUG4208224_WAR_PARAMS *pParams) {
+    return pDevice->__deviceCtrlCmdKGrInternalInitBug4208224War__(pDevice, pParams);
+}
+
 NV_STATUS deviceCtrlCmdFbGetCompbitStoreInfo_IMPL(struct Device *pDevice, NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS *pCompbitStoreParams);
 
 static inline NV_STATUS deviceCtrlCmdFbGetCompbitStoreInfo_DISPATCH(struct Device *pDevice, NV0080_CTRL_FB_GET_COMPBIT_STORE_INFO_PARAMS *pCompbitStoreParams) {

src/nvidia/generated/g_intr_nvoc.h

@@ -7,7 +7,7 @@ extern "C" {
 #endif
 
 /*
- * SPDX-FileCopyrightText: Copyright (c) 2006-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2006-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
  * SPDX-License-Identifier: MIT
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
@@ -149,6 +149,11 @@ interruptEntryIsEmpty(const InterruptEntry *pEntry)
 // Default value for intrStuckThreshold
 #define INTR_STUCK_THRESHOLD 1000
 
+// Minimum length of interrupt to log as long-running
+#define LONG_INTR_LOG_LENGTH_NS (1000000LLU) // 1ms
+// Maximum frequency of long-running interrupt print, per engine
+#define LONG_INTR_LOG_RATELIMIT_NS (10000000000LLU) // 10s
+
 #define INTR_TABLE_INIT_KERNEL (1 << 0)
 #define INTR_TABLE_INIT_PHYSICAL (1 << 1)
 
@@ -265,6 +270,13 @@ typedef struct Device Device;
 #define PRIVATE_FIELD(x) NVOC_PRIVATE_FIELD(x)
 #endif
 
+struct __nvoc_inner_struc_Intr_1__ {
+    NvU32 intrCount;
+    NvU64 intrLength;
+    NvU64 lastPrintTime;
+};
+
+
 struct Intr {
     const struct NVOC_RTTI *__nvoc_rtti;
     struct OBJENGSTATE __nvoc_base_OBJENGSTATE;
@@ -338,6 +350,7 @@ struct Intr {
     NvU32 intrEn0Orig;
     NvBool halIntrEnabled;
     NvU32 saveIntrEn0;
+    struct __nvoc_inner_struc_Intr_1__ longIntrStats[171];
 };
 
 #ifndef __NVOC_CLASS_Intr_TYPEDEF__