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chore(avalid): Rename signal to 'valid'
CI #45: Pull request #26 opened by arturum1
December 21, 2023 05:18 16s arturum1:master
December 21, 2023 05:18 16s
Merge pull request #24 from arturum1/master
CI #44: Commit 091455b pushed by PedroAntunes178
October 27, 2023 14:25 1m 19s master
October 27, 2023 14:25 1m 19s
Update regs dictionary; Remove LIB.
CI #43: Pull request #24 synchronize by arturum1
October 26, 2023 12:26 22s arturum1:master
October 26, 2023 12:26 22s
Update regs dictionary; Remove LIB.
CI #42: Pull request #24 synchronize by arturum1
October 26, 2023 11:46 17s arturum1:master
October 26, 2023 11:46 17s
Update regs dictionary; Remove LIB.
CI #41: Pull request #24 synchronize by arturum1
October 25, 2023 08:22 29s arturum1:master
October 25, 2023 08:22 29s
Merge pull request #25 from PedroAntunes178/master
CI #40: Commit 8465018 pushed by jjts
September 20, 2023 20:27 23s master
September 20, 2023 20:27 23s
submodules/LIB: update.
CI #39: Pull request #25 opened by PedroAntunes178
September 20, 2023 20:20 29s PedroAntunes178:master
September 20, 2023 20:20 29s
Update regs dictionary; Remove LIB.
CI #38: Pull request #24 opened by arturum1
September 1, 2023 18:12 1m 52s arturum1:master
September 1, 2023 18:12 1m 52s
Merge pull request #23 from arturum1/master
CI #37: Commit b74ccc1 pushed by jjts
August 9, 2023 18:59 31m 29s master
August 9, 2023 18:59 31m 29s
Update UART16550 port names to include direction suffix.
CI #36: Pull request #23 synchronize by arturum1
August 9, 2023 18:40 1m 22s arturum1:master
August 9, 2023 18:40 1m 22s
Update UART16550 port names to include direction suffix.
CI #35: Pull request #23 opened by arturum1
August 9, 2023 18:38 2m 19s arturum1:master
August 9, 2023 18:38 2m 19s
Merge pull request #22 from arturum1/master
CI #34: Commit 1a21c10 pushed by jjts
August 8, 2023 23:03 27s master
August 8, 2023 23:03 27s