.gitignore

#TOP
#nothing to ignore

#SOFTWARE
#software/periphs.h

#*.c

TAGS
.clangd
compile_commands.json
debug/

#software/pc-emul/*
#!software/pc-emul/Makefile
#!software/pc-emul/test.expected
#!software/pc-emul/testVersatSpecification.txt

#software/test/*.bin

#!software/bootloader/boot.c
#!software/bootloader/boot.S

#!software/console/console
#!software/console/eth_console

#!software/firmware/benchmarks
#!software/firmware/crypto

#HARDWARE
#sources

#hardware/include/signal_inst.vh

#hardware/src/system.v
#hardware/src/versat_instance.v
#hardware/src/GeneratedUnits/*
#hardware/testbench/system_tb.v
#hardware/include/versat_defs.vh
#scala sources
#hardware/src/spinalHDL/project/*
#hardware/src/spinalHDL/target/*

#simulation
#hardware/simulation/*/*
#!hardware/simulation/verilog_tb/*

#!hardware/simulation/simulation.mk
#!hardware/simulation/*/Makefile
#!hardware/simulation/*/*.expected
#!hardware/simulation/*/*.sh
#!hardware/simulation/verilator/*.cpp

#fpga
#hardware/fpga/*/*/*
#!hardware/fpga/fpga.mk
#!hardware/fpga/*/*/Makefile
#!hardware/fpga/*/*/*.tcl
#!hardware/fpga/*/*/*.expected
#!hardware/fpga/*/*/verilog
#!hardware/fpga/*/*/doc
#!hardware/fpga/vivado/*/*.xdc
#!hardware/fpga/quartus/*/*.sdc

#!hardware/fpga/quartus/*/qsys

#DOCUMENT
#document/*/*
#!document/*/Makefile
#!document/*/*.expected
#!document/*/*.pdf
#!document/presentation/presentation.tex