RISC-V_Processor_HB

A pipelined implementation for a RISC-V processor, implemented as project 1 for computer architecture class.

Name		Name	Last commit message	Last commit date
Latest commit History 52 Commits
ALU_control_unit.v		ALU_control_unit.v
Additional Flags.jpg		Additional Flags.jpg
Bit8Adder.v		Bit8Adder.v
Control Unit Signals.docx		Control Unit Signals.docx
DFlipFlop.v		DFlipFlop.v
DataMem.v		DataMem.v
Four_Digit_Seven_Segment_Driver.v		Four_Digit_Seven_Segment_Driver.v
InstMem.v		InstMem.v
PC_mux.v		PC_mux.v
PC_mux_module.v		PC_mux_module.v
Processor.v		Processor.v
README.md		README.md
RISCV_pipeline.v		RISCV_pipeline.v
RegFile.v		RegFile.v
branch_control.v		branch_control.v
const.xdc		const.xdc
control_unit.v		control_unit.v
decoder.v		decoder.v
decompression_unit.v		decompression_unit.v
defines.v		defines.v
forwarding_unit.v		forwarding_unit.v
fullAdder.v		fullAdder.v
mux.v		mux.v
mux_W.v		mux_W.v
n_bit_reg_file.v		n_bit_reg_file.v
prv32_ALU.v		prv32_ALU.v
rd_mux.v		rd_mux.v
rv32_ImmGen.v		rv32_ImmGen.v
shifter.v		shifter.v
tb.v		tb.v

Provide feedback