Monocycle processor (32 bits) in MIPS architecture, made in VHDL and running in the GHDL 0.33 environment. Inspired in the processor LEGv8.
- Data memory are not included in VHD files, it is inserted as ram.dat in testbench(completeProcessor_tb.vhd)
- ram.dat (Data Memory) have 2KiB.
- rom.dat (Instruction Memory) have 1 KiB.
- "Read Data" in "data memory" is inserted directly in the processor through testbench "dmem_dato_in"
- "Instruction" in "Instruction memory" is inserted directly in the processor through testbench "imem_data_in"
Instructions with their respective opcodes, formats and effects:
| Instruction | Effect/Meaning | Opcode | Format |
|---|---|---|---|
| LDUR | Load a register with memory (ram.dat) content | 11111000010 | Format D |
| STUR | Store a register content in memory (ram.dat) | 11111000000 | Format D |
| ADD | Addition the content of two registers | 10001011000 | Format R |
| SUB | Subtracts the contents of two registers | 11001011000 | Format R |
| AND | Logical AND with the contents of two registers | 10001010000 | Format R |
| ORR | Logical OR with the contents of two registers | 10101010000 | Format R |
| CBZ | Compare And Branch on Zero | 10110100 | Format CB |
| B | Inconditional Branch | 000101 | Format B |
Datapath retired from: Figure 4.11 - Computer Organization and Design by David A Patterson and John L Hennessy
Signals from the Control Unit and their respective effects within the data flow
Table retired from: Figure 4.48 - Computer Organization and Design by David A Patterson and John L Hennessy
The rom.dat (Instruction Memory) and testbench (completeProcessor_tb.vhd) is loaded with a program:
The ram.dat (Data Memory) is loaded with 3 values, they are already implemented in the testbench (completeProcessor_tb.vhd).