i#3544 RV64: Preserve vtype and vl vector registers

Applied the feedbacke recieved by reviwers Issue: #3544
DynamoRIO · Dec 17, 2024 · a8227b9 · a8227b9
1 parent efb52d0
commit a8227b9
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Showing 3 changed files with 6 additions and 34 deletions.
diff --git a/core/arch/riscv64/emit_utils.c b/core/arch/riscv64/emit_utils.c
@@ -1,5 +1,6 @@
 /* **********************************************************
  * Copyright (c) 2022 Rivos, Inc.  All rights reserved.
+ * Copyright (c) 2024 Foundation of Research and Technology, Hellas.
  * **********************************************************/
 
 /*
@@ -664,19 +665,12 @@ append_restore_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute)
                                opnd_create_reg(DR_REG_A0),
                                opnd_create_immed_int(VCSR, OPSZ_12b)));
 
-        /*
-         * The code below is contributed and copyrighted by FORTH
-         * Copyright (c) 2024 Foundation of Research and Technology, Hellas.
-         * All other rights reserved.
-         */
         APP(ilist, RESTORE_FROM_DC(dcontext, DR_REG_A0, VL_OFFSET));
         APP(ilist, RESTORE_FROM_DC(dcontext, DR_REG_A1, VTYPE_OFFSET));
         APP(ilist,
             INSTR_CREATE_vsetvl(dcontext, opnd_create_reg(DR_REG_A0),
                                 opnd_create_reg(DR_REG_A0), opnd_create_reg(DR_REG_A1)));
-        /*
-         * End of FORTH copyrighted section
-         */
+
     }
 }
 
@@ -894,11 +888,6 @@ append_save_clear_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute
                                opnd_create_immed_int(VCSR, OPSZ_12b)));
         APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VCSR_OFFSET));
 
-        /*
-         * The code below is contributed and copyrighted by FORTH
-         * Copyright (c) 2024 Foundation of Research and Technology, Hellas.
-         * All other rights reserved.
-         */
         APP(ilist,
             INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A1),
                                opnd_create_reg(DR_REG_ZERO),
@@ -909,9 +898,6 @@ append_save_clear_xflags(dcontext_t *dcontext, instrlist_t *ilist, bool absolute
                                opnd_create_reg(DR_REG_ZERO),
                                opnd_create_immed_int(VTYPE, OPSZ_12b)));
         APP(ilist, SAVE_TO_DC(dcontext, DR_REG_A1, VTYPE_OFFSET));
-        /*
-         * End of FORTH copyrighted section
-         */
     }
 }
 

diff --git a/core/arch/riscv64/mangle.c b/core/arch/riscv64/mangle.c
@@ -1,5 +1,6 @@
 /* **********************************************************
  * Copyright (c) 2022 Rivos, Inc.  All rights reserved.
+ * Copyright (c) 2024 Foundation of Research and Technology, Hellas.
  * **********************************************************/
 
 /*
@@ -193,14 +194,8 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci,
     }
 
     dstack_offs += XSP_SZ;
-
-    /*
-     * The code below is contributed and copyrighted by FORTH
-     * Copyright (c) 2024 Foundation of Research and Technology, Hellas.
-     * All other rights reserved.
-     */
+
     if (proc_has_feature(FEATURE_VECTOR)) {
-        /* csrr a0, vl */
         PRE(ilist, instr,
             INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0),
                                opnd_create_reg(DR_REG_ZERO),
@@ -213,13 +208,7 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci,
 
     dstack_offs += XSP_SZ;
 
-    /*
-     * The code below is contributed and copyrighted by FORTH
-     * Copyright (c) 2024 Foundation of Research and Technology, Hellas.
-     * All other rights reserved.
-     */
     if (proc_has_feature(FEATURE_VECTOR)) {
-        /* csrr a0, vtype */
         PRE(ilist, instr,
             INSTR_CREATE_csrrs(dcontext, opnd_create_reg(DR_REG_A0),
                                opnd_create_reg(DR_REG_ZERO),
@@ -231,9 +220,6 @@ insert_push_all_registers(dcontext_t *dcontext, clean_call_info_t *cci,
     }
 
     dstack_offs += 2 * XSP_SZ;
-    /*
-     * End of FORTH copyrighted section
-     */
 
     /* Push vector registers. */
     if (proc_has_feature(FEATURE_VECTOR)) {

diff --git a/core/lib/mcxtx_api.h b/core/lib/mcxtx_api.h
@@ -566,8 +566,8 @@
     reg_t fcsr; /**< Floating-Point Control Register. */
     reg_t vstart; /**< Vector Start Index CSR. */
     reg_t vcsr; /**< Vector Control and Status Register. */
-    reg_t vl;
-    reg_t vtype;
+    reg_t vl; /**< Vector Length Register. */
+    reg_t vtype; /**< Vector Type Register. */
     /** The Vector registers. */
     dr_simd_t simd[MCXT_NUM_SIMD_SLOTS];
 #else /* RISCV64 */