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i#3044 AArch64 SVE codec: Add predicate logical operations (#5792)
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This patch adds the appropriate macros, tests and codec entries
to encode the following variants:
AND     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
AND     <Zd>.D, <Zn>.D, <Zm>.D
ANDS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
BIC     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
BIC     <Zd>.D, <Zn>.D, <Zm>.D
BICS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
EOR     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
EOR     <Zd>.D, <Zn>.D, <Zm>.D
EORS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
NAND    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
NANDS   <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
NOR     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
NORS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
NOT     <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
ORN     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
ORNS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
ORR     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
ORR     <Zd>.D, <Zn>.D, <Zm>.D
ORRS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B

Issue #3044
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@cmannett85-arm
cmannett85-arm authored Dec 16, 2022
1 parent 614a3c9 commit 301f9ed
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Showing 6 changed files with 1,121 additions and 3 deletions.
31 changes: 31 additions & 0 deletions core/ir/aarch64/codec.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2361,6 +2361,22 @@ encode_opnd_p10(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
return encode_opnd_p(10, 15, opnd, enc_out);
}

/* p10_zer: SVE predicate registers p0-p15, zeroing */
static inline bool
decode_opnd_p10_zer(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
*opnd = opnd_create_predicate_reg(DR_REG_P0 + extract_uint(enc, 10, 4), false);
return true;
}

static inline bool
encode_opnd_p10_zer(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
if (!opnd_is_predicate_zero(opnd))
return false;
return encode_opnd_p(10, 15, opnd, enc_out);
}

/* cmode_s_sz: Operand for 32 bit elements' shift amount */

static inline bool
Expand Down Expand Up @@ -3050,6 +3066,21 @@ encode_opnd_p16_zer(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_o
return encode_opnd_p(16, 15, opnd, enc_out);
}

/* p_b_16: P register with a byte element size */
static inline bool
decode_opnd_p_b_16(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
return decode_single_sized(DR_REG_P0, 16, 4, BYTE_REG, enc, opnd);
}

static inline bool
encode_opnd_p_b_16(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
if (!opnd_is_predicate_reg(opnd))
return false;
return encode_single_sized(OPSZ_SCALABLE_PRED, 16, BYTE_REG, opnd, enc_out);
}

/* sysreg: system register, operand of MRS/MSR */

static inline bool
Expand Down
25 changes: 22 additions & 3 deletions core/ir/aarch64/codec_sve.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -45,8 +45,14 @@
00000100xx000000000xxxxxxxxxxxxx n 9 SVE add z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5
00100101xx10000011xxxxxxxxxxxxxx n 9 SVE add z_size_bhsd_0 : z_size_bhsd_0 imm8_5 lsl shift1
00000100xx011010000xxxxxxxxxxxxx n 21 SVE and z0 : p10_lo z0 z5 bhsd_sz
00000101100000xxxxxxxxxxxxxxxxxx n 21 SVE and z_imm13_bhsd_0 : z_imm13_bhsd_0 imm13_const
00000101100000xxxxxxxxxxxxxxxxxx n 21 SVE and z_imm13_bhsd_0 : z_imm13_bhsd_0 imm13_const
001001010000xxxx01xxxx0xxxx0xxxx n 21 SVE and p_b_0 : p10_zer p_b_5 p_b_16
00000100001xxxxx001100xxxxxxxxxx n 21 SVE and z_d_0 : z_d_5 z_d_16
001001010100xxxx01xxxx0xxxx0xxxx w 22 SVE ands p_b_0 : p10_zer p_b_5 p_b_16
00000100xx011011000xxxxxxxxxxxxx n 29 SVE bic z0 : p10_lo z0 z5 bhsd_sz
001001010000xxxx01xxxx0xxxx1xxxx n 29 SVE bic p_b_0 : p10_zer p_b_5 p_b_16
00000100111xxxxx001100xxxxxxxxxx n 29 SVE bic z_d_0 : z_d_5 z_d_16
001001010100xxxx01xxxx0xxxx1xxxx w 30 SVE bics p_b_0 : p10_zer p_b_5 p_b_16
00100101xx0xxxxx100xxxxxxxx0xxxx w 807 SVE cmpeq p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 simm5
00100100xx0xxxxx001xxxxxxxx0xxxx w 807 SVE cmpeq p_size_bhs_0 : p10_zer_lo z_size_bhs_5 z_d_16
00100100xx0xxxxx101xxxxxxxx0xxxx w 807 SVE cmpeq p_size_bhsd_0 : p10_zer_lo z_size_bhsd_5 z_size_bhsd_16
Expand Down Expand Up @@ -80,7 +86,10 @@
00100101xx1011011000100xxxxxxxxx n 822 SVE decp x0 : p_size_bhsd_5 x0
00100101xx1011011000000xxxxxxxxx n 822 SVE decp z_size_hsd_0 : p_size_hsd_5 z_size_hsd_0
00000100xx011001000xxxxxxxxxxxxx n 90 SVE eor z0 : p10_lo z0 z5 bhsd_sz
00000101010000xxxxxxxxxxxxxxxxxx n 90 SVE eor z_imm13_bhsd_0 : z_imm13_bhsd_0 imm13_const
00000101010000xxxxxxxxxxxxxxxxxx n 90 SVE eor z_imm13_bhsd_0 : z_imm13_bhsd_0 imm13_const
001001010000xxxx01xxxx1xxxx0xxxx n 90 SVE eor p_b_0 : p10_zer p_b_5 p_b_16
00000100101xxxxx001100xxxxxxxxxx n 90 SVE eor z_d_0 : z_d_5 z_d_16
001001010100xxxx01xxxx1xxxx0xxxx w 828 SVE eors p_b_0 : p10_zer p_b_5 p_b_16
01100101xx0xxxxx110xxxxxxxx1xxxx n 96 SVE facge p_size_hsd_0 : p10_zer_lo z_size_hsd_5 z_size_hsd_16
01100101xx0xxxxx111xxxxxxxx1xxxx n 97 SVE facgt p_size_hsd_0 : p10_zer_lo z_size_hsd_5 z_size_hsd_16
01100101xx010010001xxxxxxxx0xxxx n 102 SVE fcmeq p_size_hsd_0 : p10_zer_lo z_size_hsd_5 zero_fp_const
Expand All @@ -107,9 +116,19 @@
00000100xx0xxxxx111xxxxxxxxxxxxx n 788 SVE msb z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_16 z_size_bhsd_5
00000100xx010000000xxxxxxxxxxxxx n 321 SVE mul z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_0 z_size_bhsd_5
00100101xx110000110xxxxxxxxxxxxx n 321 SVE mul z_size_bhsd_0 : z_size_bhsd_0 simm8_5
001001011000xxxx01xxxx1xxxx1xxxx n 829 SVE nand p_b_0 : p10_zer p_b_5 p_b_16
001001011100xxxx01xxxx1xxxx1xxxx w 830 SVE nands p_b_0 : p10_zer p_b_5 p_b_16
00000100xx010111101xxxxxxxxxxxxx n 323 SVE neg z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_5
001001011000xxxx01xxxx1xxxx0xxxx n 831 SVE nor p_b_0 : p10_zer p_b_5 p_b_16
001001011100xxxx01xxxx1xxxx0xxxx w 832 SVE nors p_b_0 : p10_zer p_b_5 p_b_16
00000100xx011110101xxxxxxxxxxxxx n 325 SVE not z_size_bhsd_0 : p10_mrg_lo z_size_bhsd_5
001001011000xxxx01xxxx0xxxx1xxxx n 326 SVE orn p_b_0 : p10_zer p_b_5 p_b_16
001001011100xxxx01xxxx0xxxx1xxxx w 833 SVE orns p_b_0 : p10_zer p_b_5 p_b_16
00000100xx011000000xxxxxxxxxxxxx n 327 SVE orr z0 : p10_lo z0 z5 bhsd_sz
00000101000000xxxxxxxxxxxxxxxxxx n 327 SVE orr z_imm13_bhsd_0 : z_imm13_bhsd_0 imm13_const
00000101000000xxxxxxxxxxxxxxxxxx n 327 SVE orr z_imm13_bhsd_0 : z_imm13_bhsd_0 imm13_const
001001011000xxxx01xxxx0xxxx0xxxx n 327 SVE orr p_b_0 : p10_zer p_b_5 p_b_16
00000100011xxxxx001100xxxxxxxxxx n 327 SVE orr z_d_0 : z_d_5 z_d_16
001001011100xxxx01xxxx0xxxx0xxxx w 834 SVE orrs p_b_0 : p10_zer p_b_5 p_b_16
001001010101000011xxxx0xxxx00000 w 786 SVE ptest : p10 p_b_5
0010010100011001111100000000xxxx n 817 SVE rdffr p_b_0 :
00100101000110001111000xxxx0xxxx n 817 SVE rdffr p_b_0 : p5_zer
Expand Down
299 changes: 299 additions & 0 deletions core/ir/aarch64/instr_create_api.h
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Original file line number Diff line number Diff line change
Expand Up @@ -6714,4 +6714,303 @@
#define INSTR_CREATE_orn_sve_imm(dc, Zdn, imm) \
instr_create_1dst_2src(dc, OP_orr, Zdn, Zdn, opnd_invert_immed_int(imm))

/**
* Creates an AND instruction.
*
* This macro is used to encode the forms:
* \verbatim
* AND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
* \param Pm The second source predicate register, P (Predicate).
*/
#define INSTR_CREATE_and_sve_pred_b(dc, Pd, Pg, Pn, Pm) \
instr_create_1dst_3src(dc, OP_and, Pd, Pg, Pn, Pm)

/**
* Creates an AND instruction.
*
* This macro is used to encode the forms:
* \verbatim
* AND <Zd>.D, <Zn>.D, <Zm>.D
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Zd The destination vector register, Z (Scalable).
* \param Zn The first source vector register, Z (Scalable).
* \param Zm The second source vector register, Z (Scalable).
*/
#define INSTR_CREATE_and_sve(dc, Zd, Zn, Zm) \
instr_create_1dst_2src(dc, OP_and, Zd, Zn, Zm)

/**
* Creates an ANDS instruction.
*
* This macro is used to encode the forms:
* \verbatim
* ANDS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
* \param Pm The second source predicate register, P (Predicate).
*/
#define INSTR_CREATE_ands_sve_pred(dc, Pd, Pg, Pn, Pm) \
instr_create_1dst_3src(dc, OP_ands, Pd, Pg, Pn, Pm)

/**
* Creates a BIC instruction.
*
* This macro is used to encode the forms:
* \verbatim
* BIC <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
* \param Pm The second source predicate register, P (Predicate).
*/
#define INSTR_CREATE_bic_sve_pred_b(dc, Pd, Pg, Pn, Pm) \
instr_create_1dst_3src(dc, OP_bic, Pd, Pg, Pn, Pm)

/**
* Creates a BIC instruction.
*
* This macro is used to encode the forms:
* \verbatim
* BIC <Zd>.D, <Zn>.D, <Zm>.D
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Zd The destination vector register, Z (Scalable).
* \param Zn The first source vector register, Z (Scalable).
* \param Zm The second source vector register, Z (Scalable).
*/
#define INSTR_CREATE_bic_sve(dc, Zd, Zn, Zm) \
instr_create_1dst_2src(dc, OP_bic, Zd, Zn, Zm)

/**
* Creates a BICS instruction.
*
* This macro is used to encode the forms:
* \verbatim
* BICS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
* \param Pm The second source predicate register, P (Predicate).
*/
#define INSTR_CREATE_bics_sve_pred(dc, Pd, Pg, Pn, Pm) \
instr_create_1dst_3src(dc, OP_bics, Pd, Pg, Pn, Pm)

/**
* Creates an EOR instruction.
*
* This macro is used to encode the forms:
* \verbatim
* EOR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
* \param Pm The second source predicate register, P (Predicate).
*/
#define INSTR_CREATE_eor_sve_pred_b(dc, Pd, Pg, Pn, Pm) \
instr_create_1dst_3src(dc, OP_eor, Pd, Pg, Pn, Pm)

/**
* Creates an EOR instruction.
*
* This macro is used to encode the forms:
* \verbatim
* EOR <Zd>.D, <Zn>.D, <Zm>.D
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Zd The destination vector register, Z (Scalable).
* \param Zn The first source vector register, Z (Scalable).
* \param Zm The second source vector register, Z (Scalable).
*/
#define INSTR_CREATE_eor_sve(dc, Zd, Zn, Zm) \
instr_create_1dst_2src(dc, OP_eor, Zd, Zn, Zm)

/**
* Creates an EORS instruction.
*
* This macro is used to encode the forms:
* \verbatim
* EORS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
* \param Pm The second source predicate register, P (Predicate).
*/
#define INSTR_CREATE_eors_sve_pred(dc, Pd, Pg, Pn, Pm) \
instr_create_1dst_3src(dc, OP_eors, Pd, Pg, Pn, Pm)

/**
* Creates a NAND instruction.
*
* This macro is used to encode the forms:
* \verbatim
* NAND <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
* \param Pm The second source predicate register, P (Predicate).
*/
#define INSTR_CREATE_nand_sve_pred(dc, Pd, Pg, Pn, Pm) \
instr_create_1dst_3src(dc, OP_nand, Pd, Pg, Pn, Pm)

/**
* Creates a NANDS instruction.
*
* This macro is used to encode the forms:
* \verbatim
* NANDS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
* \param Pm The second source predicate register, P (Predicate).
*/
#define INSTR_CREATE_nands_sve_pred(dc, Pd, Pg, Pn, Pm) \
instr_create_1dst_3src(dc, OP_nands, Pd, Pg, Pn, Pm)

/**
* Creates a NOR instruction.
*
* This macro is used to encode the forms:
* \verbatim
* NOR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
* \param Pm The second source predicate register, P (Predicate).
*/
#define INSTR_CREATE_nor_sve_pred(dc, Pd, Pg, Pn, Pm) \
instr_create_1dst_3src(dc, OP_nor, Pd, Pg, Pn, Pm)

/**
* Creates a NORS instruction.
*
* This macro is used to encode the forms:
* \verbatim
* NORS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
* \param Pm The second source predicate register, P (Predicate).
*/
#define INSTR_CREATE_nors_sve_pred(dc, Pd, Pg, Pn, Pm) \
instr_create_1dst_3src(dc, OP_nors, Pd, Pg, Pn, Pm)

/**
* Creates a NOT instruction.
*
* This macro is used to encode the forms:
* \verbatim
* NOT <Zd>.<Ts>, <Pg>/M, <Zn>.<Ts>
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Zd The destination vector register, Z (Scalable).
* \param Pg The governing predicate register, P (Predicate).
* \param Zn The source vector register, Z (Scalable).
*/
#define INSTR_CREATE_not_sve_pred_vec(dc, Zd, Pg, Zn) \
instr_create_1dst_2src(dc, OP_not, Zd, Pg, Zn)

/**
* Creates an ORN instruction.
*
* This macro is used to encode the forms:
* \verbatim
* ORN <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
* \param Pm The second source predicate register, P (Predicate).
*/
#define INSTR_CREATE_orn_sve_pred(dc, Pd, Pg, Pn, Pm) \
instr_create_1dst_3src(dc, OP_orn, Pd, Pg, Pn, Pm)

/**
* Creates an ORNS instruction.
*
* This macro is used to encode the forms:
* \verbatim
* ORNS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
* \param Pm The second source predicate register, P (Predicate).
*/
#define INSTR_CREATE_orns_sve_pred(dc, Pd, Pg, Pn, Pm) \
instr_create_1dst_3src(dc, OP_orns, Pd, Pg, Pn, Pm)

/**
* Creates an ORR instruction.
*
* This macro is used to encode the forms:
* \verbatim
* ORR <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
* \param Pm The second source predicate register, P (Predicate).
*/
#define INSTR_CREATE_orr_sve_pred_b(dc, Pd, Pg, Pn, Pm) \
instr_create_1dst_3src(dc, OP_orr, Pd, Pg, Pn, Pm)

/**
* Creates an ORR instruction.
*
* This macro is used to encode the forms:
* \verbatim
* ORR <Zd>.D, <Zn>.D, <Zm>.D
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Zd The destination vector register, Z (Scalable).
* \param Zn The first source vector register, Z (Scalable).
* \param Zm The second source vector register, Z (Scalable).
*/
#define INSTR_CREATE_orr_sve(dc, Zd, Zn, Zm) \
instr_create_1dst_2src(dc, OP_orr, Zd, Zn, Zm)

/**
* Creates an ORRS instruction.
*
* This macro is used to encode the forms:
* \verbatim
* ORRS <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
* \endverbatim
* \param dc The void * dcontext used to allocate memory for the #instr_t.
* \param Pd The destination predicate register, P (Predicate).
* \param Pg The governing predicate register, P (Predicate).
* \param Pn The first source predicate register, P (Predicate).
* \param Pm The second source predicate register, P (Predicate).
*/
#define INSTR_CREATE_orrs_sve_pred(dc, Pd, Pg, Pn, Pm) \
instr_create_1dst_3src(dc, OP_orrs, Pd, Pg, Pn, Pm)

#endif /* DR_IR_MACROS_AARCH64_H */
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