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Take into account higher allowable H7 VCO speed on V model
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David-OConnor committed Sep 4, 2021
1 parent b0f7e00 commit 70ab51e
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Showing 2 changed files with 11 additions and 8 deletions.
2 changes: 1 addition & 1 deletion Cargo.toml
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
[package]
name = "stm32-hal2"
version = "1.0.1"
version = "1.0.2"
authors = ["David O'Connor <[email protected]>"]
description = "Hardware abstraction layer for the STM32 MCUs"
keywords = ["no-std", "stm32", "embedded", "embedded-hal"]
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17 changes: 10 additions & 7 deletions src/clocks/h7.rs
Original file line number Diff line number Diff line change
Expand Up @@ -172,30 +172,30 @@ impl VosRange {
185_000_001..=210_000_000 => (2, 2),
210_000_001..=225_000_000 => (3, 2),
225_000_001..=240_000_000 => (4, 2),
_ => panic!("Can't set higher than 240Mhz HCLK with VSO0 range."),
_ => panic!("Can't set higher than 240Mhz HCLK with VSO0 range. (Try changing the `vos_range` setting)."),
},
Self::VOS1 => match hclk {
0..=70_000_000 => (0, 0),
70_000_001..=140_000_000 => (1, 1),
140_000_001..=185_000_000 => (2, 1),
185_000_001..=210_000_000 => (2, 2),
210_000_001..=225_000_000 => (3, 2),
_ => panic!("Can't set higher than 225Mhz HCLK with VOS1 range."),
_ => panic!("Can't set higher than 225Mhz HCLK with VOS1 range. (Try changing the `vos_range` setting)."),
},
Self::VOS2 => match hclk {
0..=55_000_000 => (0, 0),
55_000_001..=110_000_000 => (1, 1),
110_000_001..=165_000_000 => (2, 1),
165_000_001..=225_000_000 => (3, 2),
_ => panic!("Can't set higher than 225Mhz HCLK with VSO2 range."),
_ => panic!("Can't set higher than 225Mhz HCLK with VSO2 range. (Try changing the `vos_range` setting)."),
},
Self::VOS3 => match hclk {
0..=45_000_000 => (0, 0),
45_000_001..=90_000_000 => (1, 1),
90_000_001..=135_000_000 => (2, 1),
135_000_001..=180_000_000 => (3, 2),
180_000_001..=225_000_000 => (4, 2),
_ => panic!("Can't set higher than 225Mhz HCLK with VSO3 range."),
_ => panic!("Can't set higher than 225Mhz HCLK with VSO3 range. (Try changing the `vos_range` setting)."),
},
}
}
Expand Down Expand Up @@ -295,7 +295,7 @@ impl Clocks {
match self.vos_range {
#[cfg(not(feature = "h7b3"))]
VosRange::VOS0 => {
// VOS0 activation/deactivation sequence
// VOS0 activation/deactivation sequence: H743 HRM, section 6.6.2:
// The system maximum frequency can be reached by boosting the voltage scaling level to
// VOS0. This is done through the ODEN bit in the SYSCFG_PWRCR register.
// The sequence to activate the VOS0 is the following:
Expand All @@ -315,7 +315,7 @@ impl Clocks {
if #[cfg(any(feature = "h747cm4", feature = "h747cm7"))] {
syscfg.pwrcr.modify(|_, w| w.oden().set_bit());
} else {
syscfg.pwrcr.write(|w| unsafe { w.oden().bits(1) });
syscfg.pwrcr.modify(|_, w| unsafe { w.oden().bits(1) });
}
}

Expand Down Expand Up @@ -560,6 +560,7 @@ impl Clocks {
}
}

#[cfg(not(feature = "h7b3"))]
rcc.d2ccip1r.modify(|_, w| unsafe {
w.sai1sel().bits(self.sai1_src as u8);
w.sai23sel().bits(self.sai23_src as u8)
Expand Down Expand Up @@ -770,8 +771,10 @@ impl Clocks {
return Err(SpeedError::new("Invalid PLL input speed"));
}
// VCO0: Wide VCO range: 192 to 836 MHz (default after reset) (VCOH)
// Note: The RM appears out of date: Revision "V" allgedly supports 960_000_000
// VCO speed, to allow a max core speed of 480Mhz.
let vco_speed = self.vco_output_freq(pll_src, 1);
if pll_input_speed <= 2_000_000 && (vco_speed < 192_000_000 || vco_speed > 836_000_000)
if pll_input_speed <= 2_000_000 && (vco_speed < 192_000_000 || vco_speed > 960_000_000)
{
return Err(SpeedError::new("Invalid wide VCO speed"));
}
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