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Merge branch 'cabal_tsu_async' into 'devel'
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refactor(net-mod): use component TSU_ASYNC instead of removed TS_SYNC

See merge request ndk/ndk-fpga!132
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jakubcabal committed Jan 9, 2025
2 parents 3039513 + a5972da commit 9e857a3
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Showing 14 changed files with 144 additions and 637 deletions.
53 changes: 10 additions & 43 deletions comp/tsu/tsu_async/Modules.tcl
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@@ -1,49 +1,16 @@
# Modules.tcl: Local include Modules tcl script
# Copyright (C) 2009 CESNET
# Author: Jan Stourac <xstour03 at stud.fit.vutbr.cz>
# Jiri Matousek <[email protected]>
# Modules.tcl: Components include script
# Copyright (C) 2025 CESNET z.s.p.o.
# Author(s): Jakub Cabal <[email protected]>
#
# SPDX-License-Identifier: BSD-3-Clause
#


# Auxiliary paths
set BASE_BASE "$COMP_BASE/base"

# Component paths
set ASFIFO_BASE "$OFM_PATH/comp/base/fifo/asfifo"

# Paths to subcomponents with scoped constraints
set ASYNC_OPEN_LOOP_SMD_BASE "$OFM_PATH/comp/base/async/open_loop_smd"

# Use source files of the module
if { $ARCHGRP == "SRC" } {
# Components
set COMPONENTS [list \
[list "ASFIFO" $ASFIFO_BASE "FULL"] \
]

# Modules
set MOD "$MOD $ENTITY_BASE/tsu_async.vhd"
}

# Use .dcp file of the module
# (Add also all subcomponents with scoped constraints. This hack is necessary
# for correct constraint's application in full design.)
if { $ARCHGRP == "DCP" } {
# Components
set COMPONENTS [ list \
[list "ASYNC_OPEN_LOOP_SMD" $ASYNC_OPEN_LOOP_SMD_BASE "FULL"] \
[list "ASFIFO" $ASFIFO_BASE "FULL"] \
]
# Paths
set ASFIFOX_BASE "$OFM_PATH/comp/base/fifo/asfifox"

# Modules
set MOD "$MOD $ENTITY_BASE/synth/tsu_async.dcp"
# Packages

# All device tree scripts used by module
if { [file exists "$ENTITY_BASE/synth/DevTree_paths.txt"] } {
set MOD "$MOD [read [open "$ENTITY_BASE/synth/DevTree_paths.txt" "r"]]"
}
}
# Components
lappend COMPONENTS [list "ASFIFOX" $ASFIFOX_BASE "FULL"]

lappend SRCS(CONSTR_VIVADO) [list $ENTITY_BASE/tsu_async_ooc.xdc USED_IN {synthesis out_of_context}]
# Files
lappend MOD "$ENTITY_BASE/tsu_async.vhd"
32 changes: 0 additions & 32 deletions comp/tsu/tsu_async/sim/comp_sig.fdo

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16 changes: 0 additions & 16 deletions comp/tsu/tsu_async/sim/signals.fdo

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40 changes: 0 additions & 40 deletions comp/tsu/tsu_async/sim/testbench.fdo

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103 changes: 0 additions & 103 deletions comp/tsu/tsu_async/sim/testbench.vhd

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27 changes: 0 additions & 27 deletions comp/tsu/tsu_async/sim/tsu_async.fdo

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20 changes: 0 additions & 20 deletions comp/tsu/tsu_async/sim/tsu_async_sig.fdo

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50 changes: 7 additions & 43 deletions comp/tsu/tsu_async/synth/Makefile
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@@ -1,47 +1,11 @@
# Makefile: Makefile to synthesize a single component in Vivado
# Copyright (C) 2016 CESNET
# Author: Jiri Matousek <matousek@cesnet.cz>
# Makefile: Makefile to compile module
# Copyright (C) 2025 CESNET z.s.p.o.
# Author(s): Jakub Cabal <cabal@cesnet.cz>
#
# SPDX-License-Identifier: BSD-3-Clause
#
# $Id$
#


# ##### Definition of variables ###############################################

# Basic paths
OFM_PATH = ../../../../..

# Tcl file with NetCOPE values for generic parameters
# (if defined, uses the value from top level Makefile)
NETCOPE_CONST ?=

# Tcl file with user-defined values for generic parameters
# (if defined, uses the value from top level Makefile)
USER_CONST ?=

# Definition of export command for selected variables used by build system
# (variable used in $(OFM_PATH)/build/Makefile.Vivado.inc)
USER_ENV = OFM_PATH=$(OFM_PATH) \
NETCOPE_CONST=$(NETCOPE_CONST) \
USER_CONST=$(USER_CONST)

# Module name
# (variable used also in $(OFM_PATH)/build/Makefile.Vivado.inc)
MODULE = tsu_async


# ##### Definition of targets #################################################

.PHONY: build_module

build_module : $(MODULE).dcp


# ##### Including another Makefiles ###########################################
TOP_LEVEL_ENT=TSU_ASYNC

# General Makefile for builds using Vivado
# * defines target for building *.dcp file
# * defines 'clean' target depending also on CLEAN_DEPENDS variable
include $(OFM_PATH)/build/Makefile.Vivado.inc
all: comp
include ../../../../build/Makefile
.PHONY: all
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