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18 followers · 17 following
  • Member at RISC-V International
  • BIT Mesra, Jharkhand, India

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@EEESocbitmesra

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Amrit-Raj-Official/README.md

Amrit_Raj

Hi, I'm Amrit Raj

A VLSI frontend enthusiast.

  • Fun fact: Playing with 1s and 0s.

  • Skills: RTL Coding, RISC-V, Verilog (HDL), System Verilog (HVL), C, Python, UVM Framework.

  • Certifications: Siemens EDA System Verilog and UVM Certified & Red Hat Certified System Administrator (RHCSA v8.0).

Connect with me:

https://www.linkedin.com/in/amrit-raj-623962173/amritraj46@gmail.com

Languages and Tools:

Verilog System Verilog Red Hat c UVM EDA Playground python RISC-V

Popular repositories Loading

  1. 32-bit-Instruction-Word-Register 32-bit-Instruction-Word-Register Public

    SystemVerilog 1 1

  2. risc-processor risc-processor Public

    Forked from jcsison/risc-processor

    Verilog implementation of a 16-bit RISC processor designed around a basic instruction set.

    Verilog 1

  3. Amrit-Raj-Official Amrit-Raj-Official Public

    1

  4. FIFO_Mem FIFO_Mem Public

    Forked from EEESocbitmesra/FIFO_Mem

    SystemVerilog 1

  5. UART-master UART-master Public

    Forked from EEESocbitmesra/UART-master

    SystemVerilog 1

  6. E-yantra-Audio-Processing E-yantra-Audio-Processing Public

    Python 1