5.0.0
Status: November 2024
The 5.0.0 release is the first stable release in the 5.x series. The main new feature over the 4.x series is support for the Arm Scalable Vector Extensions (SVE) SIMD instruction set, with both 128-bit and 256-bit backends provided. This gives up to 60% performance improvement on Neoverse V2 with its 256-bit SVE implementation.
- General:
- Bug fix: Fixed incorrect return type in "None" vector library reference implementation.
- Bug fix: Fixed sincos table index under/overflow.
- Feature: Changed
ASTCENC_ISA_NATIVE
builds to use-march=native
and-mcpu=native
. - Feature: Added backend for Arm SVE fixed-width 256-bit builds. These can only run on hardware implementing 256-bit SVE.
- Feature: Added backend for Arm SVE 128-bit builds. These are portable builds and can run on hardware implementing any SVE vector length, but the explicit SVE use is augmented NEON and will only use the bottom 128-bits of each SVE vector.
- Feature: Optimized NEON mask
any()
andall()
functions. - Feature: Migrated build and test to GitHub Actions pipelines.
Binary release sha256 checksums
70183c4346f9fc0f55cd8e3ca5b326cbb4675233b026c02df60657e344c44cc0 astcenc-5.0.0-linux-x64.zip
b8e450250932f07765d868318709964da2a36d41be0538f5c018d8fc72a41e70 astcenc-5.0.0-macos-universal.zip
dbaf1a1329f6fd909457b43e7872092e979ba8ebd9bdf9dbbd950069fa533124 astcenc-5.0.0-windows-arm64.zip
6c22b89f3d437d457c45036c8297ce9cec400f8bdfa019eed71e3b8d343f5ebb astcenc-5.0.0-windows-x64.zip