Removed some doxygen warnings

CMSIS/Core/Include/armv7r.h

@@ -197,7 +197,7 @@
 #define     __IOM    volatile            /*!< \brief Defines 'read / write' structure member permissions */
 #define RESERVED(N, T) T RESERVED##N;    // placeholder struct members used for "reserved" areas
 
-/*@} end of group ARMv7-R */
+/** @} end of group ARMv7-R */
 
 
 

CMSIS/Core/Include/armv8a.h

@@ -257,7 +257,7 @@
 #define     __IOM    volatile            /*!< \brief Defines 'read / write' structure member permissions */
 #define RESERVED(N, T) T RESERVED##N;    // placeholder struct members used for "reserved" areas
 
-/*@} end of group ARMv8-A */
+/** @} end of group ARMv8-A */
 
 
 

CMSIS/Core/Include/armv8r.h

@@ -252,7 +252,7 @@
 #define     __IOM    volatile            /*!< \brief Defines 'read / write' structure member permissions */
 #define RESERVED(N, T) T RESERVED##N;    // placeholder struct members used for "reserved" areas
 
-/*@} end of group ARMv8-R */
+/** @} end of group ARMv8-R */
 
 
 

CMSIS/Core/Include/cmsis_armcc.h

@@ -469,9 +469,9 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(in
   /**
     \brief   Unsigned Saturate
     \details Saturates an unsigned value.
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
+    \param [in]  val  Value to be saturated
+    \param [in]  sat  Bit position to saturate to (0..31)
+    \return           Saturated value
    */
   __attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat)
   {
@@ -493,7 +493,7 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(in
           (defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
           (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
 
-/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+/** @} end of group CMSIS_Core_InstructionInterface */
 
 
 /* ###########################  Core Function Access  ########################### */
@@ -516,24 +516,24 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(in
  */
 /* intrinsic void __disable_irq(void); */
 
-#if ((defined (__arm__         ) || \
+#if ((defined (__arm__         )) || \
      (defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
      (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     )
 
-/**
-  \brief   Enable FIQ
-  \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
-           Can only be executed in Privileged modes.
- */
-#define __enable_fault_irq                __enable_fiq
+  /**
+    \brief   Enable FIQ
+    \details Enables FIQ interrupts by clearing special-purpose register FAULTMASK.
+             Can only be executed in Privileged modes.
+   */
+  #define __enable_fault_irq                __enable_fiq
 
 
-/**
-  \brief   Disable FIQ
-  \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
-           Can only be executed in Privileged modes.
- */
-#define __disable_fault_irq               __disable_fiq
+  /**
+    \brief   Disable FIQ
+    \details Disables FIQ interrupts by setting special-purpose register FAULTMASK.
+             Can only be executed in Privileged modes.
+   */
+  #define __disable_fault_irq               __disable_fiq
 
 #endif /* ( defined (__arm__         ) || \
            (defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__  == 1)) || \
@@ -653,6 +653,6 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
 
   #define __SXTAB16_RORn(ARG1, ARG2, ARG3) __SXTAB16(ARG1, __ROR(ARG2, ARG3))
 #endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1))     ) */
-/*@} end of group CMSIS_SIMD_intrinsics */
+/** @} end of group CMSIS_SIMD_intrinsics */
 
 #endif /* __CMSIS_ARMCC_H */

CMSIS/Core/Include/cmsis_armclang.h

@@ -490,9 +490,9 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
   /**
     \brief   Unsigned Saturate
     \details Saturates an unsigned value.
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
+    \param [in]  val  Value to be saturated
+    \param [in]  sat  Bit position to saturate to (0..31)
+    \return           Saturated value
    */
   __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
   {

CMSIS/Core/Include/cmsis_armclang_ltm.h

@@ -498,9 +498,9 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
   /**
     \brief   Unsigned Saturate
     \details Saturates an unsigned value.
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
+    \param [in]  val  Value to be saturated
+    \param [in]  sat  Bit position to saturate to (0..31)
+    \return           Saturated value
    */
   __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
   {

CMSIS/Core/Include/cmsis_gcc.h

@@ -629,9 +629,9 @@ __STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value)
   /**
     \brief   Unsigned Saturate
     \details Saturates an unsigned value.
-    \param [in]  value  Value to be saturated
-    \param [in]    sat  Bit position to saturate to (0..31)
-    \return             Saturated value
+    \param [in]  val  Value to be saturated
+    \param [in]  sat  Bit position to saturate to (0..31)
+    \return           Saturated value
    */
   __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
   {

CMSIS/Core/Include/cmsis_tiarmclang_corem.h

@@ -551,9 +551,9 @@ __STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat)
 /**
   \brief   Unsigned Saturate
   \details Saturates an unsigned value.
-  \param [in]  value  Value to be saturated
-  \param [in]    sat  Bit position to saturate to (0..31)
-  \return             Saturated value
+  \param [in]  val  Value to be saturated
+  \param [in]  sat  Bit position to saturate to (0..31)
+  \return           Saturated value
  */
 __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
 {

CMSIS/CoreValidation/Layer/Target/CA5/RTE/Device/ARMCA5/mmu_ARMCA5.c

@@ -145,7 +145,7 @@ void MMU_CreateTranslationTable(void)
     MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);
 
     /*
-     * Generate descriptors. Refer to core_ca.h to get information about attributes
+     * Generate descriptors. Refer to armv7a.h to get information about attributes
      *
      */
     //Create descriptors for Vectors, RO, RW, ZI sections

CMSIS/CoreValidation/Layer/Target/CA7/RTE/Device/ARMCA7/mmu_ARMCA7.c

@@ -145,7 +145,7 @@ void MMU_CreateTranslationTable(void)
     MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);
 
     /*
-     * Generate descriptors. Refer to core_ca.h to get information about attributes
+     * Generate descriptors. Refer to armv7a.h to get information about attributes
      *
      */
     //Create descriptors for Vectors, RO, RW, ZI sections

CMSIS/CoreValidation/Layer/Target/CA9/RTE/Device/ARMCA9/mmu_ARMCA9.c

@@ -145,7 +145,7 @@ void MMU_CreateTranslationTable(void)
     MMU_TTSection (TTB_BASE, 0, 4096, DESCRIPTOR_FAULT);
 
     /*
-     * Generate descriptors. Refer to core_ca.h to get information about attributes
+     * Generate descriptors. Refer to armv7a.h to get information about attributes
      *
      */
     //Create descriptors for Vectors, RO, RW, ZI sections

CMSIS/DoxyGen/Core/Core.dxy.in

@@ -47,7 +47,7 @@ PROJECT_NAME           = "CMSIS-Core (Cortex-M)"
 # could be handy for archiving the generated documentation or if some version
 # control system is used.
 
-PROJECT_NUMBER         = "Version 5.7.0"
+PROJECT_NUMBER         = "Version 6.0.0"
 
 # Using the PROJECT_BRIEF tag one can provide an optional one line description
 # for a project that appears at the top of each page and should give viewer a

CMSIS/DoxyGen/Core_A/Core_A.dxy.in

@@ -47,7 +47,7 @@ PROJECT_NAME           = "CMSIS-Core (Cortex-A)"
 # could be handy for archiving the generated documentation or if some version
 # control system is used.
 
-PROJECT_NUMBER         = "Version 1.2.1"
+PROJECT_NUMBER         = "Version 6.0.0"
 
 # Using the PROJECT_BRIEF tag one can provide an optional one line description
 # for a project that appears at the top of each page and should give viewer a
@@ -920,18 +920,22 @@ INPUT                  = src/Overview.txt \
                          src/Using.txt \
                          src/Template.txt \
                          src/MISRA.txt \
-                         ../../Core_A/Include/core_ca.h \
-                         ../../Core_A/Include/cmsis_armcc.h \
-                         ../../Core_A/Include/cmsis_cp15.h \
-                         ../../Core_A/Source/irq_ctrl_gic.c \
-                         ../../Core_A/Include/irq_ctrl.h \
+                         ../../Core/Include/cmsis_version.h \
+                         ../../Core/Include/armv7a.h \
+                         ../../Core/Include/armv7a_cp15.h \
+                         ../../Core/Include/armv8a.h \
+                         ../../Core/Include/cmsis_armcc.h \
+                         ../../Core/Include/cmsis_armcc_corea.h \
+                         ../../Core/Include/gic_v20.h \
+                         ../../Core/Source/irq_ctrl_gic.c \
+                         ../../Core/Include/irq_ctrl.h \
                          src/Ref_SystemAndClock.txt \
                          src/ref_gic.txt \
                          src/ref_core_register.txt \
                          src/ref_cache.txt \
                          src/ref_timer.txt \
                          src/ref_mmu.txt \
-                         src/core_ca.txt \
+                         src/arm7a.txt \
                          src/cmsis_armcc.txt \
                          src/irq_ctrl.txt \
 

CMSIS/DoxyGen/Core_A/src/Overview.txt

@@ -26,7 +26,7 @@ Files relevant to CMSIS-Core (Cortex-A) are present in the following <b>ARM::CMS
 |File/Folder                     |Content                                                                 |
 |--------------------------------|------------------------------------------------------------------------|
 |\b CMSIS\\Documentation\\Core_A | This documentation                                                     |
-|\b CMSIS\\Core_A\\Include       | CMSIS-Core (Cortex-A) header files (for example core_ca.h, etc.)                |
+|\b CMSIS\\Core\\Include         | CMSIS-Core (Cortex-A) header files (for example core_ca5.h, etc.)      |
 |\b Device                       | \ref using_ARM_pg "Arm reference implementations" of Cortex-A devices  |
 |\b Device\\\_Template_Vendor    | \ref templates_pg for extension by silicon vendors                     |
 

CMSIS/DoxyGen/Core_A/src/Template.txt

@@ -6,6 +6,7 @@
 Arm supplies CMSIS-Core device template files for the all supported Cortex-A processors and various compiler vendors.
 Refer to the list of \ref tested_tools_sec for compliance.
 
+
 These CMSIS-Core device template files include the following:
  - Register names of the Core Peripherals and names of the Core Exception Vectors.
  - Functions to access core peripherals, cache, MMU and special CPU instructions 
@@ -15,26 +16,32 @@ The detailed file structure of the CMSIS-Core device templates is shown in the f
 
 <!-- \image html "CMSIS_CORE_Files.png" "CMSIS-Core File Structure" -->
 
-\section CMSIS_Processor_files CMSIS-Core Processor Files 
+\section CMSIS_Processor_files CMSIS-Core Processor Files
 
-The CMSIS-Core processor files provided by Arm are in the directory .\\CMSIS\\Core_A\\Include. These header files define all processor specific attributes do not need any modifications.
+The CMSIS-Core processor files provided by Arm are in the directory .\\CMSIS\\Core\\Include. These header files define all processor specific attributes do not need any modifications.
 The <b>core_&lt;cpu&gt;.h</b> defines the core peripherals and provides helper functions that access the core registers. One file is available for each supported Cortex-A processor:
 
 Header File      | Processor
 :----------------|:------------------------------
-core_ca.h        | generics for all supported Cortex-A processors
-
+core_ca5.h       | for the Cortex-A5 processor
+core_ca7.h       | for the Cortex-A7 processor
+core_ca9.h       | for the Cortex-A9 processor
+core_ca35.h      | for the Cortex-A35 processor
+core_ca53.h      | for the Cortex-A53 processor
+core_ca57.h      | for the Cortex-A57 processor
 \section device_examples Device Examples
 
 The CMSIS Software Pack defines several devices that are based on the various processors. The device related CMSIS-Core files are in the directory .\\Device\\ARM
 and include CMSIS-Core processor file explained before. The following sample devices are defined in the CMSIS-Pack description file <b>ARM.CMSIS.pdsc</b>:
 
-Family             | Device            | Description
-:------------------|:------------------|:---------------------------------
-ARM Cortex-A5      | ARMCA5            | Cortex-A5 based device
-ARM Cortex-A7      | ARMCA7            | Cortex-A7 based device
-ARM Cortex-A9      | ARMCA9            | Cortex-A9 based device
-
+Family            | Device            | Description
+:-----------------|:------------------|:---------------------------------
+ARM Cortex-A5     | ARMCA5            | Cortex-A5 based device
+ARM Cortex-A7     | ARMCA7            | Cortex-A7 based device
+ARM Cortex-A9     | ARMCA9            | Cortex-A9 based device
+ARM Cortex-A35    | ARMCA35           | Cortex-A35 based device
+ARM Cortex-A53    | ARMCA53           | Cortex-A53 based device
+ARM Cortex-A57    | ARMCA57           | Cortex-A57 based device
 
 
 \section template_files_sec Template Files
@@ -53,7 +60,7 @@ Silicon vendors add to these template files the following information:
     <tr>
       <td>.\\Device\\\_Template_Vendor\\Vendor\\Device_A\\Source\\ARM\\startup_Device.c</td>
       <td>Startup file template for Arm C/C++ Compiler.</td>
-    </tr>   
+    </tr>
     <tr>
       <td>.\\Device\\\_Template_Vendor\\Vendor\\Device_A\\Source\\ARM\\Device.sct</td>
       <td>Linker scatter file template for Arm C/C++ Compiler.</td>
@@ -129,9 +136,10 @@ The device configuration of the template files is described in detail on the fol
 \page startup_c_pg Startup File startup_<device>.c
 
 The \ref startup_c_pg contains:
- - Exception vectors of the Cortex-A Processor with weak functions that implement default routines.
  - The reset handler which is executed after CPU reset and typically calls the \ref SystemInit function.
  - The setup values for the various stack pointers, i.e. per exceptional mode and main stack.
+ - Exception vectors of the Cortex-A Processor with weak functions that implement default routines.
+ - Interrupt vectors that are device specific with weak functions that implement default routines.
 
 The file exists for each supported toolchain and is the only tool-chain specific CMSIS file.
 
@@ -238,7 +246,7 @@ If these <i>\#defines</i> are missing default values are used.
       <th>Description</th>
     </tr>
     <tr>
-      <td>__CM0_REV</td>
+      <td>__CA5_REV</td>
       <td>0x0000</td>
       <td>0x0000</td>
       <td>Core revision number ([15:8] revision number, [7:0] patch number)</td>
@@ -286,9 +294,9 @@ The following code exemplifies the configuration of the Cortex-A9 Processor and
 #define __GIC_PRESENT        1U    /*!< GIC present                                 */
 #define __TIM_PRESENT        0U    /*!< TIM not present                             */
 #define __L2C_PRESENT        0U    /*!< L2C not present                             */
-:
-:
-#include "core_ca.h"               /* Cortex-A processor and core peripherals       */
+.
+.
+#include "core_ca9.h"              /* Cortex-A processor and core peripherals       */
 \endcode
 
 

CMSIS/DoxyGen/Core_A/src/core_ca.txt → CMSIS/DoxyGen/Core_A/src/arm7a.txt

@@ -1,5 +1,5 @@
 /**************************************************************************//**
- * @file     core_ca.txt
+ * @file     arm7a.txt
  * @brief    CMSIS Cortex-A Core Peripheral Access Layer Header File
  ******************************************************************************/
 
@@ -79,7 +79,7 @@ The registers in the various UARTs can now be referred in the user code as shown
 
 \section core_cmsis_pal_min_reqs Minimal Requirements
 \details
- To access the peripheral registers and related function in a device, the files <b><i>device.h</i></b> and <b>core_ca.h</b> define as a minimum:
+ To access the peripheral registers and related function in a device, the files <b><i>device.h</i></b> and <b>armv7a.h</b> define as a minimum:
 \n\n
 - The <b>Register Layout Typedef</b> for each peripheral that defines all register names.
   RESERVED is used to introduce space into the structure for adjusting the addresses of