* Retire the Core_A folder and use a single Core folder for all proce…

…ssor core headers.

* Separate folders for different architecture profiles (A-profile, R-profile and M-profile)
* Top-level compiler headers will exist in the Core folder (no separate Compiler folder is needed).
** The cmsis_compiler.h header will continue to figure out which compiler toolchain is being used.
** The compiler toolchain specific headers in the Core folder will contain code common to all architecture profiles.
** Compiler headers specific to each architecture profiles can reside within the new architecture profile folders.
** The second-level files like cmsis_gcc.h are named cmsis_gcc_a.h, cmsis_gcc_r.h and cmsis_gcc_m.h to avoid having multiple files with the same name
*For any features that are common to more than one architecture profile, e.g, the GIC is common to A-profile and R-profile, we can include the GIC header in each architectural folder, but only one of these files contains the code to avoid duplication. The file with the same name that doesn't include the code will simply include the code from the other folder- this should hopefully be clear to developers.
* removed deprecated core_armv8xxx.h files. The files were added because no specific ARM v8-M device was available when Arm v-M support was added.
* removed deprecated file cmsis_armcc_a.h. This compiler support is obsolete
Add initial support for some Cortex-A and Cortex-R devices

CMSIS/Core/Include/a-profile/cmsis_cp15.h → CMSIS/Core/Include/a-profile/armv7a_cp15.h

@@ -1,11 +1,11 @@
 /**************************************************************************//**
- * @file     cmsis_cp15.h
+ * @file     armv7a_cp15.h
  * @brief    CMSIS compiler specific macros, functions, instructions
  * @version  V1.0.2
  * @date     19. December 2022
  ******************************************************************************/
 /*
- * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
+ * Copyright (c) 2009-2023 ARM Limited. All rights reserved.
  *
  * SPDX-License-Identifier: Apache-2.0
  *

CMSIS/Core/Include/a-profile/armv8a_system_control.h

@@ -0,0 +1,143 @@
+/**************************************************************************//**
+ * @file     armv8a_system_control.h
+ * @brief    CMSIS compiler specific macros, functions, instructions
+ * @version  V6.0.0
+ * @date     4. August 2023
+ ******************************************************************************/
+/*
+ * Copyright (c) 2009-2023 ARM Limited. All rights reserved.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the License); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an AS IS BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdint.h>
+
+ #if   defined ( __ICCARM__ )
+  #pragma system_include         /* treat file as system include file for MISRA check */
+#elif defined (__clang__)
+  #pragma clang system_header   /* treat file as system include file */
+#endif
+
+#ifndef __CMSIS_SYSTEM_CONTROL_H
+#define __CMSIS_SYSTEM_CONTROL_H
+
+
+  /** \brief  Get MPIDR EL1
+      \return Multiprocessor Affinity Register value
+   */
+  __STATIC_FORCEINLINE uint64_t __get_MPIDR_EL1(void)
+  {
+    uint64_t result;
+    __ASM volatile("MRS %0, MPIDR_EL1" : "=r" (result) : : "memory");
+    return result;
+  }
+
+  /** \brief  Get MAIR EL3
+      \return               MAIR value
+   */
+  __STATIC_FORCEINLINE uint64_t __get_MAIR_EL3(void)
+  {
+    uint64_t result;
+    __ASM volatile("MRS  %0, mair_el3" : "=r" (result) : : "memory");
+    return result;
+  }
+
+  /** \brief  Set MAIR EL3
+      \param [in]    mair  MAIR value to set
+   */
+  __STATIC_FORCEINLINE void __set_MAIR_EL3(uint64_t mair)
+  {
+    __ASM volatile("MSR  mair_el3, %0" : : "r" (mair) : "memory");
+  }
+
+  /** \brief  Get TCR EL3
+      \return               TCR value
+   */
+  __STATIC_FORCEINLINE uint64_t __get_TCR_EL3(void)
+  {
+    uint64_t result;
+    __ASM volatile("MRS  %0, tcr_el3" : "=r" (result) : : "memory");
+    return result;
+  }
+
+  /** \brief  Set TCR EL3
+      \param [in]    tcr  TCR value to set
+   */
+  __STATIC_FORCEINLINE void __set_TCR_EL3(uint64_t tcr)
+  {
+    __ASM volatile("MSR  tcr_el3, %0" : : "r" (tcr) : "memory");
+  }
+
+  /** \brief  Get TTBR0 EL3
+      \return               Translation Table Base Register 0 value
+   */
+  __STATIC_FORCEINLINE uint64_t __get_TTBR0_EL3(void)
+  {
+    uint64_t result;
+    __ASM volatile("MRS  %0, ttbr0_el3" : "=r" (result) : : "memory");
+    return result;
+  }
+
+  /** \brief  Set TTBR0 EL3
+      \param [in]    ttbr0  Translation Table Base Register 0 value to set
+   */
+  __STATIC_FORCEINLINE void __set_TTBR0_EL3(uint64_t ttbr0)
+  {
+    __ASM volatile("MSR  ttbr0_el3, %0" : : "r" (ttbr0) : "memory");
+  }
+
+  /** \brief  Get SCTLR EL3
+      \return STRLR EL3 value
+   */
+  __STATIC_FORCEINLINE uint64_t __get_SCTLR_EL3(void)
+  {
+    uint64_t result;
+    __ASM volatile("MRS  %0, sctlr_el3" : "=r" (result) : : "memory");
+    return result;
+  }
+
+  /** \brief  Set SCTLR EL3
+      \param [in]    vbar  SCTLR value to set
+   */
+  __STATIC_FORCEINLINE void __set_SCTLR_EL3(uint64_t sctlr)
+  {
+    __ASM volatile("MSR  sctlr_el3, %0" : : "r" (sctlr) : "memory");
+  }
+
+  /** \brief  Set VBAR EL3
+      \param [in]    vbar  VBAR value to set
+   */
+  __STATIC_FORCEINLINE void __set_VBAR_EL3(uint64_t vbar)
+  {
+    __ASM volatile("MSR  vbar_el3, %0" : : "r" (vbar) : "memory");
+  }
+
+  /** \brief  Set VBAR EL2
+      \param [in]    vbar  VBAR value to set
+   */
+  __STATIC_FORCEINLINE void __set_VBAR_EL2(uint64_t vbar)
+  {
+    __ASM volatile("MSR  vbar_el2, %0" : : "r" (vbar) : "memory");
+  }
+
+  /** \brief  Set VBAR EL1
+      \param [in]    vbar  VBAR value to set
+   */
+  __STATIC_FORCEINLINE void __set_VBAR_EL1(uint64_t vbar)
+  {
+    __ASM volatile("MSR  vbar_el1, %0" : : "r" (vbar) : "memory");
+  }
+
+
+#endif /* __CMSIS_SYSTEM_CONTROL_H */