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Make the IRQ Table extern definable.
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This makes the IRQ-table extern definable. With this it is possible to define Interrupt Service Routines in the CMSIS way with week defined IRQ-Routines which can be overridden in the application code.

Example:
// …
__attribute__ ((weak, alias("InteruptDefaultHandler"))) void CoreTimer_IRQHandler (void);
// …

IRQHandler_t IRQTable [IRQ_GIC_LINE_COUNT] =
{
// …
CoreTimer_IRQHandler
// …
};

In Addition a default IRQ-Handler is implemented which calls the Interrupt-Service-Routine.
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Masmiseim36 authored Nov 3, 2022
1 parent a8c2f93 commit dd4ab4f
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Showing 2 changed files with 24 additions and 9 deletions.
2 changes: 1 addition & 1 deletion ARM.CMSIS.pdsc
Original file line number Diff line number Diff line change
Expand Up @@ -2207,7 +2207,7 @@ and 8-bit Java bytecodes in Jazelle state.
</component>

<!-- IRQ Controller -->
<component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Capiversion="1.0.0" Cversion="1.0.1" condition="ARMv7-A Device">
<component Cclass="Device" Cgroup="IRQ Controller" Csub="GIC" Capiversion="1.0.0" Cversion="1.2.0" condition="ARMv7-A Device">
<description>IRQ Controller implementation using GIC</description>
<files>
<file category="sourceC" name="CMSIS/Core_A/Source/irq_ctrl_gic.c"/>
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31 changes: 23 additions & 8 deletions CMSIS/Core_A/Source/irq_ctrl_gic.c
Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
/**************************************************************************//**
* @file irq_ctrl_gic.c
* @brief Interrupt controller handling implementation for GIC
* @version V1.1.1
* @date 29. March 2021
* @version V1.2.0
* @date 30. October 2022
******************************************************************************/
/*
* Copyright (c) 2017-2021 ARM Limited. All rights reserved.
* Copyright (c) 2017-2022 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
Expand Down Expand Up @@ -36,17 +36,23 @@
#define IRQ_GIC_LINE_COUNT (1020U)
#endif

#ifndef IRQ_GIC_EXTERN_IRQ_TABLE
static IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT] = { 0U };
#else
extern IRQHandler_t IRQTable[IRQ_GIC_LINE_COUNT];
#endif
static uint32_t IRQ_ID0;

/// Initialize interrupt controller.
__WEAK int32_t IRQ_Initialize (void) {
uint32_t i;
#ifndef IRQ_GIC_EXTERN_IRQ_TABLE
uint32_t i;

for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
IRQTable[i] = (IRQHandler_t)NULL;
}
GIC_Enable();
for (i = 0U; i < IRQ_GIC_LINE_COUNT; i++) {
IRQTable[i] = (IRQHandler_t)NULL;
}
GIC_Enable();
#endif
return (0);
}

Expand All @@ -65,6 +71,15 @@ __WEAK int32_t IRQ_SetHandler (IRQn_ID_t irqn, IRQHandler_t handler) {
return (status);
}

/// The Interrupt Handler.
__WEAK void IRQ_Handler (void) {
IRQn_Type irqn = GIC_AcknowledgePending ();
if (irqn < (IRQn_Type)IRQ_GIC_LINE_COUNT) {
IrqTable[irqn]();

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@JonatanAntoni

JonatanAntoni Nov 4, 2022

Member

@Masmiseim36, this went through the review. May I ask you to provide a fix, please?

}
GIC_EndInterrupt (irqn);
}


/// Get the registered interrupt handler.
__WEAK IRQHandler_t IRQ_GetHandler (IRQn_ID_t irqn) {
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