diff --git a/.github/workflows/west_cmds.yml b/.github/workflows/west_cmds.yml index 73d942cadfe3d5..d7b671bc7e7f12 100644 --- a/.github/workflows/west_cmds.yml +++ b/.github/workflows/west_cmds.yml @@ -66,7 +66,7 @@ jobs: - name: install pytest run: | pip3 install wheel - pip3 install pytest west pyelftools canopen natsort progress mypy intelhex psutil ply pyserial + pip3 install pytest west pyelftools canopen natsort progress mypy intelhex psutil ply pyserial anytree - name: run pytest-win if: runner.os == 'Windows' run: | diff --git a/arch/arm/include/cortex_m/exception.h b/arch/arm/include/cortex_m/exception.h index 94491a71b3fcc4..c021d59d76411e 100644 --- a/arch/arm/include/cortex_m/exception.h +++ b/arch/arm/include/cortex_m/exception.h @@ -258,7 +258,7 @@ static ALWAYS_INLINE void z_arm_set_fault_sp(const struct arch_esf *esf, uint32_ } #endif /* CONFIG_FPU && CONFIG_FPU_SHARING */ -#ifndef CONFIG_ARMV8_M_MAINLINE +#if !(defined(CONFIG_ARMV8_M_MAINLINE) || defined(CONFIG_ARMV8_M_BASELINE)) if ((esf->basic.xpsr & SCB_CCR_STKALIGN_Msk) == SCB_CCR_STKALIGN_Msk) { /* Adjust stack alignment after PSR bit[9] detected */ z_arm_coredump_fault_sp |= 0x4; diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts index e232445e811a64..dc702bf2a7661f 100644 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts +++ b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4.dts @@ -9,13 +9,28 @@ #include #include "cy8ckit_062_ble_common.dtsi" +#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi" / { model = "Cypress PSoC6 BLE Pioneer Kit"; compatible = "cypress,cy8c6xx7_cm4", "cypress,psoc6"; + aliases { + uart-6 = &uart6; + }; + chosen { zephyr,sram = &sram2; zephyr,flash = &flash1; + zephyr,console = &uart6; + zephyr,shell-uart = &uart6; }; }; + +&uart6 { + status = "okay"; + current-speed = <115200>; + + pinctrl-0 = <&p13_0_scb6_uart_rx &p13_1_scb6_uart_tx>; + pinctrl-names = "default"; +}; diff --git a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay b/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay deleted file mode 100644 index 26f422a9b4dc38..00000000000000 --- a/boards/cypress/cy8ckit_062_ble/cy8ckit_062_ble_cy8c6347_m4_0_0_0.overlay +++ /dev/null @@ -1,26 +0,0 @@ -/* - * Copyright (c) 2021, ATL Electronics - * - * SPDX-License-Identifier: Apache-2.0 - */ - -#include "cy8ckit_062_ble_cy8c6347-pinctrl.dtsi" - -/ { - aliases { - uart-6 = &uart6; - }; - - chosen { - zephyr,console = &uart6; - zephyr,shell-uart = &uart6; - }; -}; - -&uart6 { - status = "okay"; - current-speed = <115200>; - - pinctrl-0 = <&p13_0_scb6_uart_rx &p13_1_scb6_uart_tx>; - pinctrl-names = "default"; -}; diff --git a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig index 221643eca2791e..2bda7847628abd 100644 --- a/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig +++ b/boards/infineon/cy8cproto_062_4343w/cy8cproto_062_4343w_defconfig @@ -17,9 +17,6 @@ CONFIG_UART_CONSOLE=y # Enable UART driver CONFIG_SERIAL=y -# Enable GPIO driver -CONFIG_GPIO=y - # Enable clock controller CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig index 7d0d29ea39cc9f..98136255552ab5 100644 --- a/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig +++ b/boards/infineon/cy8cproto_063_ble/cy8cproto_063_ble_defconfig @@ -18,9 +18,6 @@ CONFIG_UART_CONSOLE=y # Enable UART driver CONFIG_SERIAL=y -# Enable GPIO -CONFIG_GPIO=y - # Enable clock controller CONFIG_CLOCK_CONTROL=y diff --git a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig index 426cd85d30f371..14c80355800304 100644 --- a/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig +++ b/boards/infineon/cyw920829m2evk_02/cyw920829m2evk_02_defconfig @@ -18,9 +18,6 @@ CONFIG_UART_CONSOLE=y # Enable UART driver CONFIG_SERIAL=y -# Enable GPIO driver -CONFIG_GPIO=y - # Enable clock controller CONFIG_CLOCK_CONTROL=y diff --git a/boards/lilygo/ttgo_lora32/doc/index.rst b/boards/lilygo/ttgo_lora32/doc/index.rst index bb80805c39b4d5..4a0ae0a5dde13e 100644 --- a/boards/lilygo/ttgo_lora32/doc/index.rst +++ b/boards/lilygo/ttgo_lora32/doc/index.rst @@ -1,7 +1,4 @@ -.. _ttgo_lora32: - -Lilygo TTGO LoRa32 -################## +.. zephyr:board:: ttgo_lora32 Overview ******** @@ -18,13 +15,6 @@ It's available in two versions supporting two different frequency ranges and fea Some of the ESP32 I/O pins are accessible on the board's pin headers. -.. figure:: img/ttgo_lora32.webp - :align: center - :alt: Lilygo TTGO LoRa32 module - :width: 400 px - - Lilygo TTGO LoRa32 module - Functional Description ********************** diff --git a/boards/lilygo/ttgo_t8c3/doc/index.rst b/boards/lilygo/ttgo_t8c3/doc/index.rst index a2aa6934a6d027..4179528b6af576 100644 --- a/boards/lilygo/ttgo_t8c3/doc/index.rst +++ b/boards/lilygo/ttgo_t8c3/doc/index.rst @@ -1,7 +1,4 @@ -.. _ttgo_t8c3: - -Lilygo TTGO T8-C3 -################# +.. zephyr:board:: ttgo_t8c3 Overview ******** @@ -17,12 +14,6 @@ It features the following integrated components: - JST GH 2-pin battery connector - LED -.. figure:: img/ttgo_t8c3.webp - :align: center - :alt: TTGO T8-C3 - - Lilygo TTGO T8-C3 - Functional Description ********************** This board is based on the ESP32-C3 with 4MB of flash, WiFi and BLE support. It diff --git a/boards/nxp/mimxrt700_evk/CMakeLists.txt b/boards/nxp/mimxrt700_evk/CMakeLists.txt new file mode 100644 index 00000000000000..e13f3a26796306 --- /dev/null +++ b/boards/nxp/mimxrt700_evk/CMakeLists.txt @@ -0,0 +1,28 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0 OR CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1) + zephyr_library() + zephyr_library_sources(board.c) +endif() + +if(CONFIG_NXP_IMXRT_BOOT_HEADER) + if(NOT ((DEFINED CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0) + OR (DEFINED CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1))) + message(WARNING "It appears you are using the board definition for " + "the MIMXRT7xx-EVK, but targeting a custom board. You may need to " + "update your flash configuration block data") + endif() + # Include flash configuration block for RT7xx EVK from NXP's HAL. + # This configuration block may need modification if another flash chip is + # used on your custom board. See NXP AN13304 for more information. + zephyr_compile_definitions(BOOT_HEADER_ENABLE=1) + zephyr_compile_definitions(BOARD_FLASH_SIZE=CONFIG_FLASH_SIZE*1024) + set(RT7XX_BOARD_DIR + "${ZEPHYR_HAL_NXP_MODULE_DIR}/mcux/mcux-sdk/boards/mimxrt700evk") + zephyr_library_sources(${RT7XX_BOARD_DIR}/flash_config/flash_config.c) + zephyr_library_include_directories(${RT7XX_BOARD_DIR}/flash_config) +endif() diff --git a/boards/nxp/mimxrt700_evk/Kconfig.mimxrt700_evk b/boards/nxp/mimxrt700_evk/Kconfig.mimxrt700_evk new file mode 100644 index 00000000000000..af33cfc734b4e7 --- /dev/null +++ b/boards/nxp/mimxrt700_evk/Kconfig.mimxrt700_evk @@ -0,0 +1,7 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_MIMXRT700_EVK + select SOC_MIMXRT798S_CM33_CPU0 if BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0 + select SOC_MIMXRT798S_CM33_CPU1 if BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU1 + select SOC_PART_NUMBER_MIMXRT798SGFOA diff --git a/boards/nxp/mimxrt700_evk/board.c b/boards/nxp/mimxrt700_evk/board.c new file mode 100644 index 00000000000000..c622e88924eeb4 --- /dev/null +++ b/boards/nxp/mimxrt700_evk/board.c @@ -0,0 +1,389 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ +#include +#include +#include "fsl_power.h" +#include "fsl_clock.h" +#include +#include + +/*!< System oscillator settling time in us */ +#define SYSOSC_SETTLING_US 220U +/*!< xtal frequency in Hz */ +#define XTAL_SYS_CLK_HZ 24000000U + +#define SET_UP_FLEXCOMM_CLOCK(x) \ + do { \ + CLOCK_AttachClk(kFCCLK0_to_FLEXCOMM##x); \ + RESET_ClearPeripheralReset(kFC##x##_RST_SHIFT_RSTn); \ + CLOCK_EnableClock(kCLOCK_LPFlexComm##x); \ + } while (0) + +const clock_main_pll_config_t g_mainPllConfig_clock_init = { + .main_pll_src = kCLOCK_MainPllOscClk, /* OSC clock */ + .numerator = 0, /* Numerator of the SYSPLL0 fractional loop divider is 0 */ + .denominator = 1, /* Denominator of the SYSPLL0 fractional loop divider is 1 */ + .main_pll_mult = kCLOCK_MainPllMult22 /* Divide by 22 */ +}; + +const clock_audio_pll_config_t g_audioPllConfig_clock_init = { + .audio_pll_src = kCLOCK_AudioPllOscClk, /* OSC clock */ + .numerator = 5040, /* Numerator of the Audio PLL fractional loop divider is 0 */ + .denominator = 27000, /* Denominator of the Audio PLL fractional loop divider is 1 */ + .audio_pll_mult = kCLOCK_AudioPllMult22, /* Divide by 22 */ + .enableVcoOut = true}; + +static void BOARD_InitAHBSC(void); + +void board_early_init_hook(void) +{ +#if CONFIG_SOC_MIMXRT798S_CM33_CPU0 + const clock_fro_config_t froAutotrimCfg = { + .targetFreq = 300000000U, + .range = 50U, + .trim1DelayUs = 15U, + .trim2DelayUs = 15U, + .refDiv = 1U, + .enableInt = 0U, + .coarseTrimEn = true, + }; + +#ifndef CONFIG_IMXRT7XX_CODE_CACHE + CACHE64_DisableCache(CACHE64_CTRL0); +#endif + + POWER_DisablePD(kPDRUNCFG_PD_LPOSC); + + /* Power up OSC */ + POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL); + /* Enable system OSC */ + CLOCK_EnableSysOscClk(true, true, SYSOSC_SETTLING_US); + /* Sets external XTAL OSC freq */ + CLOCK_SetXtalFreq(XTAL_SYS_CLK_HZ); + + /* Make sure FRO1 is enabled. */ + POWER_DisablePD(kPDRUNCFG_PD_FRO1); + + /* Switch to FRO1 for safe configure. */ + CLOCK_AttachClk(kFRO1_DIV1_to_COMPUTE_BASE); + CLOCK_AttachClk(kCOMPUTE_BASE_to_COMPUTE_MAIN); + CLOCK_SetClkDiv(kCLOCK_DivCmptMainClk, 1U); + CLOCK_AttachClk(kFRO1_DIV1_to_RAM); + CLOCK_SetClkDiv(kCLOCK_DivComputeRamClk, 1U); + CLOCK_AttachClk(kFRO1_DIV1_to_COMMON_BASE); + CLOCK_AttachClk(kCOMMON_BASE_to_COMMON_VDDN); + CLOCK_SetClkDiv(kCLOCK_DivCommonVddnClk, 1U); + +#if CONFIG_FLASH_MCUX_XSPI_XIP + /* Change to common_base clock(Sourced by FRO1). */ + xspi_clock_safe_config(); +#endif + + /* Ungate all FRO clock. */ + POWER_DisablePD(kPDRUNCFG_GATE_FRO0); + /* Use close loop mode. */ + CLOCK_EnableFroClkFreqCloseLoop(FRO0, &froAutotrimCfg, kCLOCK_FroAllOutEn); + /* Enable FRO0 MAX clock for all domains.*/ + CLOCK_EnableFro0ClkForDomain(kCLOCK_AllDomainEnable); + + CLOCK_InitMainPll(&g_mainPllConfig_clock_init); + CLOCK_InitMainPfd(kCLOCK_Pfd0, 20U); /* 475 MHz */ + CLOCK_InitMainPfd(kCLOCK_Pfd1, 24U); /* 396 MHz */ + CLOCK_InitMainPfd(kCLOCK_Pfd2, 18U); /* 528 MHz */ + /* Main PLL kCLOCK_Pfd3 (528 * 18 / 19) = 500 MHz -need 2 div -> 250 MHz*/ + CLOCK_InitMainPfd(kCLOCK_Pfd3, 19U); + + CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd0, kCLOCK_AllDomainEnable); + CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd1, kCLOCK_AllDomainEnable); + CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd2, kCLOCK_AllDomainEnable); + CLOCK_EnableMainPllPfdClkForDomain(kCLOCK_Pfd3, kCLOCK_AllDomainEnable); + + CLOCK_SetClkDiv(kCLOCK_DivCmptMainClk, 2U); + CLOCK_AttachClk(kMAIN_PLL_PFD0_to_COMPUTE_MAIN); /* Switch to PLL 237.5 MHz */ + + CLOCK_SetClkDiv(kCLOCK_DivMediaMainClk, 2U); + CLOCK_AttachClk(kMAIN_PLL_PFD0_to_MEDIA_MAIN); /* Switch to PLL 237.5 MHz */ + + CLOCK_SetClkDiv(kCLOCK_DivMediaVddnClk, 2U); + CLOCK_AttachClk(kMAIN_PLL_PFD0_to_MEDIA_VDDN); /* Switch to PLL 237.5 MHz */ + + CLOCK_SetClkDiv(kCLOCK_DivComputeRamClk, 2U); + CLOCK_AttachClk(kMAIN_PLL_PFD0_to_RAM); /* Switch to PLL 237.5 MHz */ + + CLOCK_SetClkDiv(kCLOCK_DivCommonVddnClk, 2U); + CLOCK_AttachClk(kMAIN_PLL_PFD3_to_COMMON_VDDN); /* Switch to 250MHZ */ + + /* Configure Audio PLL clock source. */ + CLOCK_InitAudioPll(&g_audioPllConfig_clock_init); /* 532.48MHZ */ + CLOCK_InitAudioPfd(kCLOCK_Pfd1, 24U); /* 399.36MHz */ + CLOCK_InitAudioPfd(kCLOCK_Pfd3, 26U); /* Enable Audio PLL PFD3 clock to 368.64MHZ */ + CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd1, kCLOCK_AllDomainEnable); + CLOCK_EnableAudioPllPfdClkForDomain(kCLOCK_Pfd3, kCLOCK_AllDomainEnable); + +#if CONFIG_FLASH_MCUX_XSPI_XIP + /* Call function xspi_setup_clock() to set user configured clock for XSPI. */ + xspi_setup_clock(XSPI0, 3U, 1U); /* Main PLL PDF1 DIV1. */ +#endif /* CONFIG_FLASH_MCUX_XSPI_XIP */ + +#elif CONFIG_SOC_MIMXRT798S_CM33_CPU1 + /* Power up OSC in case it's not enabled. */ + POWER_DisablePD(kPDRUNCFG_PD_SYSXTAL); + /* Enable system OSC */ + CLOCK_EnableSysOscClk(true, true, SYSOSC_SETTLING_US); + /* Sets external XTAL OSC freq */ + CLOCK_SetXtalFreq(XTAL_SYS_CLK_HZ); + + CLOCK_AttachClk(kFRO1_DIV3_to_SENSE_BASE); + CLOCK_SetClkDiv(kCLOCK_DivSenseMainClk, 1); + CLOCK_AttachClk(kSENSE_BASE_to_SENSE_MAIN); + + POWER_DisablePD(kPDRUNCFG_GATE_FRO2); + CLOCK_EnableFroClkFreq(FRO2, 300000000U, kCLOCK_FroAllOutEn); + + CLOCK_EnableFro2ClkForDomain(kCLOCK_AllDomainEnable); + + CLOCK_AttachClk(kFRO2_DIV3_to_SENSE_BASE); + CLOCK_SetClkDiv(kCLOCK_DivSenseMainClk, 1); + CLOCK_AttachClk(kSENSE_BASE_to_SENSE_MAIN); +#endif /* CONFIG_SOC_MIMXRT798S_CM33_CPU0 */ + + BOARD_InitAHBSC(); + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(iopctl0), okay) + RESET_ClearPeripheralReset(kIOPCTL0_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_Iopctl0); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(iopctl1), okay) + RESET_ClearPeripheralReset(kIOPCTL1_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_Iopctl1); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(iopctl2), okay) + RESET_ClearPeripheralReset(kIOPCTL2_RST_SHIFT_RSTn); + CLOCK_EnableClock(kCLOCK_Iopctl2); +#endif + +#ifdef CONFIG_BOARD_MIMXRT700_EVK_MIMXRT798S_CM33_CPU0 + CLOCK_AttachClk(kOSC_CLK_to_FCCLK0); + CLOCK_SetClkDiv(kCLOCK_DivFcclk0Clk, 1U); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm0), okay) + SET_UP_FLEXCOMM_CLOCK(0); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm1), okay) + SET_UP_FLEXCOMM_CLOCK(1); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm2), okay) + SET_UP_FLEXCOMM_CLOCK(2); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm3), okay) + SET_UP_FLEXCOMM_CLOCK(3); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm4), okay) + SET_UP_FLEXCOMM_CLOCK(4); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm5), okay) + SET_UP_FLEXCOMM_CLOCK(5); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm6), okay) + SET_UP_FLEXCOMM_CLOCK(6); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm7), okay) + SET_UP_FLEXCOMM_CLOCK(7); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm8), okay) + SET_UP_FLEXCOMM_CLOCK(8); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm9), okay) + SET_UP_FLEXCOMM_CLOCK(9); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm10), okay) + SET_UP_FLEXCOMM_CLOCK(10); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm11), okay) + SET_UP_FLEXCOMM_CLOCK(11); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm12), okay) + SET_UP_FLEXCOMM_CLOCK(12); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm13), okay) + SET_UP_FLEXCOMM_CLOCK(13); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi14), okay) + CLOCK_EnableClock(kCLOCK_LPSpi14); + RESET_ClearPeripheralReset(kLPSPI14_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpi2c15), okay) + CLOCK_EnableClock(kCLOCK_LPI2c15); + RESET_ClearPeripheralReset(kLPI2C15_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(lpspi16), okay) + CLOCK_AttachClk(kFRO0_DIV1_to_LPSPI16); + CLOCK_SetClkDiv(kCLOCK_DivLpspi16Clk, 1U); + CLOCK_EnableClock(kCLOCK_LPSpi16); + RESET_ClearPeripheralReset(kLPSPI16_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm17), okay) + CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM17); + CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm17Clk, 4U); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm18), okay) + CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM18); + CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm18Clk, 4U); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm19), okay) + CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM19); + CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm19Clk, 4U); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(flexcomm20), okay) + CLOCK_AttachClk(kSENSE_BASE_to_FLEXCOMM20); + CLOCK_SetClkDiv(kCLOCK_DivLPFlexComm20Clk, 4U); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay) + CLOCK_EnableClock(kCLOCK_Gpio0); + RESET_ClearPeripheralReset(kGPIO0_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay) + CLOCK_EnableClock(kCLOCK_Gpio1); + RESET_ClearPeripheralReset(kGPIO1_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio2), okay) + CLOCK_EnableClock(kCLOCK_Gpio2); + RESET_ClearPeripheralReset(kGPIO2_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio3), okay) + CLOCK_EnableClock(kCLOCK_Gpio3); + RESET_ClearPeripheralReset(kGPIO3_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio4), okay) + CLOCK_EnableClock(kCLOCK_Gpio4); + RESET_ClearPeripheralReset(kGPIO4_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio5), okay) + CLOCK_EnableClock(kCLOCK_Gpio5); + RESET_ClearPeripheralReset(kGPIO5_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio6), okay) + CLOCK_EnableClock(kCLOCK_Gpio6); + RESET_ClearPeripheralReset(kGPIO6_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio7), okay) + CLOCK_EnableClock(kCLOCK_Gpio7); + RESET_ClearPeripheralReset(kGPIO7_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio8), okay) + CLOCK_EnableClock(kCLOCK_Gpio8); + RESET_ClearPeripheralReset(kGPIO8_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio9), okay) + CLOCK_EnableClock(kCLOCK_Gpio9); + RESET_ClearPeripheralReset(kGPIO9_RST_SHIFT_RSTn); +#endif + +#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio10), okay) + CLOCK_EnableClock(kCLOCK_Gpio10); + RESET_ClearPeripheralReset(kGPIO10_RST_SHIFT_RSTn); +#endif +} + +static void GlikeyWriteEnable(GLIKEY_Type *base, uint8_t idx) +{ + (void)GLIKEY_SyncReset(base); + + (void)GLIKEY_StartEnable(base, idx); + (void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP1); + (void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP2); + (void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP3); + (void)GLIKEY_ContinueEnable(base, GLIKEY_CODEWORD_STEP_EN); +} + +static void GlikeyClearConfig(GLIKEY_Type *base) +{ + (void)GLIKEY_SyncReset(base); +} + +/* Disable the secure check for AHBSC and enable periperhals/sram access for masters */ +static void BOARD_InitAHBSC(void) +{ +#if defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0) + GlikeyWriteEnable(GLIKEY0, 1U); + AHBSC0->MISC_CTRL_DP_REG = 0x000086aa; + /* AHBSC0 MISC_CTRL_REG, disable Privilege & Secure checking. */ + AHBSC0->MISC_CTRL_REG = 0x000086aa; + + GlikeyWriteEnable(GLIKEY0, 7U); + /* Enable arbiter0 accessing SRAM */ + AHBSC0->COMPUTE_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF; + AHBSC0->SENSE_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF; + AHBSC0->MEDIA_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF; + AHBSC0->NPU_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF; + AHBSC0->HIFI4_ARB0RAM_ACCESS_ENABLE = 0x3FFFFFFF; +#endif + + GlikeyWriteEnable(GLIKEY1, 1U); + AHBSC3->MISC_CTRL_DP_REG = 0x000086aa; + /* AHBSC3 MISC_CTRL_REG, disable Privilege & Secure checking.*/ + AHBSC3->MISC_CTRL_REG = 0x000086aa; + + GlikeyWriteEnable(GLIKEY1, 9U); + /* Enable arbiter1 accessing SRAM */ + AHBSC3->COMPUTE_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF; + AHBSC3->SENSE_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF; + AHBSC3->MEDIA_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF; + AHBSC3->NPU_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF; + AHBSC3->HIFI4_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF; + AHBSC3->HIFI1_ARB1RAM_ACCESS_ENABLE = 0x3FFFFFFF; + + GlikeyWriteEnable(GLIKEY1, 8U); + /* Access enable for COMPUTE domain masters to common APB peripherals.*/ + AHBSC3->COMPUTE_APB_PERIPHERAL_ACCESS_ENABLE = 0xffffffff; + AHBSC3->SENSE_APB_PERIPHERAL_ACCESS_ENABLE = 0xffffffff; + GlikeyWriteEnable(GLIKEY1, 7U); + AHBSC3->COMPUTE_AIPS_PERIPHERAL_ACCESS_ENABLE = 0xffffffff; + AHBSC3->SENSE_AIPS_PERIPHERAL_ACCESS_ENABLE = 0xffffffff; + + GlikeyWriteEnable(GLIKEY2, 1U); + /*Disable secure and secure privilege checking. */ + AHBSC4->MISC_CTRL_DP_REG = 0x000086aa; + AHBSC4->MISC_CTRL_REG = 0x000086aa; + +#if defined(CONFIG_SOC_MIMXRT798S_CM33_CPU0) + GlikeyClearConfig(GLIKEY0); +#endif + GlikeyClearConfig(GLIKEY1); + GlikeyClearConfig(GLIKEY2); +} diff --git a/boards/nxp/mimxrt700_evk/board.cmake b/boards/nxp/mimxrt700_evk/board.cmake new file mode 100644 index 00000000000000..2ea53e1674115f --- /dev/null +++ b/boards/nxp/mimxrt700_evk/board.cmake @@ -0,0 +1,21 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if(CONFIG_SOC_MIMXRT798S_CM33_CPU0) + board_runner_args(jlink "--device=MIMXRT798S_M33_0" "--reset-after-load") + board_runner_args(linkserver "--device=MIMXRT798S:MIMXRT700-EVK") + board_runner_args(linkserver "--override=/device/memory/4=") + board_runner_args(linkserver "--core=cm33_core0") +elseif(CONFIG_SOC_MIMXRT798S_CM33_CPU1) + board_runner_args(jlink "--device=MIMXRT798S_M33_1") + board_runner_args(linkserver "--device=MIMXRT798S:MIMXRT700-EVK") + board_runner_args(linkserver "--core=cm33_core1") +else() + message(FATAL_ERROR "Requested core is not supported") +endif() + +include(${ZEPHYR_BASE}/boards/common/jlink.board.cmake) +include(${ZEPHYR_BASE}/boards/common/linkserver.board.cmake) diff --git a/boards/nxp/mimxrt700_evk/board.yml b/boards/nxp/mimxrt700_evk/board.yml new file mode 100644 index 00000000000000..9ccd3c804b2c9f --- /dev/null +++ b/boards/nxp/mimxrt700_evk/board.yml @@ -0,0 +1,5 @@ +board: + name: mimxrt700_evk + vendor: nxp + socs: + - name: mimxrt798s diff --git a/boards/nxp/mimxrt700_evk/doc/index.rst b/boards/nxp/mimxrt700_evk/doc/index.rst new file mode 100644 index 00000000000000..84f4b3c6130cbd --- /dev/null +++ b/boards/nxp/mimxrt700_evk/doc/index.rst @@ -0,0 +1,199 @@ +.. _mimxrt700_evk: + +NXP MIMXRT700-EVK +################## + +Overview +******** + +The new i.MX RT700 CPU architecture is composed of a high-performance main compute subsystem, +a secondary “always-on” sense-compute subsystem and specialized coprocessors. + +The main compute subsystem uses a 325 MHz capable Arm® Cortex®-M33 (CM33). +Similar to the i.MX RT600 crossover MCU, the i.MX RT700 includes a Cadence Tensilica® HiFi 4 DSP. +The HiFi 4 is a high performance DSP core based upon a Very Long Instruction Word (VLIW) architecture, +which is capable of processing up to eight 32x16 MACs per instruction cycle. It can be used for offloading +high-performance numerical tasks such as audio and image processing and supports both fixed-point and +floating-point operations. + +Hardware +******** + +- Main Compute Subsystem: + Arm Cortex-M33 up to 325 MHz + HiFi 4 DSP up to 325 MHz + eIQ Neutron NPU up to 325 MHz +- Sense Compute Subsystem: + Arm Cortex-M33 up to 250 MHz + HiFi 1 DSP up to 250 MHz +- 7.5 MB on-chip SRAM +- Three xSPI interfaces for off-chip memory expansion, supporting up to 16b wide external memories up to 250 MHz DDR +- eUSB support with integrated PHY +- Two SD/eMMC memory card interfaces—one supporting eMMC 5.0 with HS400/DDR operation +- USB high-speed host/device controller with on-chip PHY +- A digital microphone interface supporting up to 8 channels +- Serial peripherals (UART/I²C/I3C/SPI/HSPI/SAI) +- 2.5D GPU with vector graphics acceleration and frame buffer compression +- EZH-V using RISC-V core with additional SIMD/DSP instructions +- Full openVG 1.1 support +- Up to 720p@60FPS from on-chip SRAM +- LCD Interface + MIPI DSI +- Integrated JPEG and PNG support +- CSI 8/10/16-bit parallel (via FlexIO) + +For more information about the MIMXRT798 SoC and MIMXRT700-EVK board, see +these references: + +- `i.MX RT700 Website`_ + +Supported Features +================== + +NXP considers the MIMXRT700-EVK as a superset board for the i.MX RT7xx +family of MCUs. This board is a focus for NXP's Full Platform Support for +Zephyr, to better enable the entire RT7xx family. NXP prioritizes enabling +this board with new support for Zephyr features. The ``mimxrt700_evk/mimxrt798s +/cm33_cpu0`` or ``mimxrt700_evk/mimxrt798s/cm33_cpu1`` board configuration supports +the hardware features below. + ++-----------+------------+-------------------------------------+ +| Interface | Controller | Driver/Component | ++===========+============+=====================================+ +| NVIC | on-chip | nested vector interrupt controller | ++-----------+------------+-------------------------------------+ +| SYSTICK | on-chip | systick | ++-----------+------------+-------------------------------------+ +| IOCON | on-chip | pinmux | ++-----------+------------+-------------------------------------+ +| GPIO | on-chip | gpio | ++-----------+------------+-------------------------------------+ +| UART | on-chip | serial port-polling; | +| | | serial port-interrupt | ++-----------+------------+-------------------------------------+ +| CLOCK | on-chip | clock_control | ++-----------+------------+-------------------------------------+ + +The default configuration can be found in the defconfig file: + + :zephyr_file:`boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0_defconfig` + :zephyr_file:`boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1_defconfig` + +Other hardware features are not currently supported by the port. + +Connections and IOs +=================== + +The MIMXRT798 SoC has IOCON registers, which can be used to configure the +functionality of a pin. + ++---------+-----------------+----------------------------+ +| Name | Function | Usage | ++=========+=================+============================+ +| PIO0_31 | UART0 | UART RX | ++---------+-----------------+----------------------------+ +| PIO1_0 | UART0 | UART TX | ++---------+-----------------+----------------------------+ +| PIO0_18 | GPIO | GREEN LED | ++---------+-----------------+----------------------------+ +| PIO0_9 | GPIO | SW5 | ++---------+-----------------+----------------------------+ +| PIO8_14 | UART19 | UART TX | ++---------+-----------------+----------------------------+ +| PIO8_15 | UART19 | UART RX | ++---------+-----------------+----------------------------+ + +System Clock +============ + +The MIMXRT700 EVK is configured to use the Systick +as a source for the system clock. + +Programming and Debugging +************************* + +Build and flash applications as usual (see :ref:`build_an_application` and +:ref:`application_run` for more details). + +Configuring a Debug Probe +========================= + +A debug probe is used for both flashing and debugging the board. This board is +configured by default to use the MCU-Link CMSIS-DAP Onboard Debug Probe. + +Using LinkServer +---------------- + +The Linkserver runner supports the factory default MCU-Link firmware. Follow +the instructions in :ref:`mcu-link-cmsis-onboard-debug-probe` to reprogram +the default MCU-Link firmware. This only needs to be done if the default onboard +debug circuit firmware was changed. To put the board in ``DFU mode`` to program +the firmware, short jumper J20. + +.. code-block:: console + + west flash -r linkserver + +Using J-Link +------------ + +There are two options. The onboard debug circuit can be updated with Segger +J-Link firmware by following the instructions in +:ref:`mcu-link-jlink-onboard-debug-probe`. +To be able to program the firmware, you need to put the board in ``DFU mode`` +by shortening the jumper J20. +The second option is to attach a :ref:`jlink-external-debug-probe` to the +20-pin SWD connector (J18) of the board. Additionally, the jumper JP18 must +be shortened. +For both options use the ``-r jlink`` option with west to use the jlink runner. + +Configuring a Console +===================== + +Connect a USB cable from your PC to J54, and use the serial terminal of your choice +(minicom, putty, etc.) with the following settings: + +- Speed: 115200 +- Data: 8 bits +- Parity: None +- Stop bits: 1 + +Flashing +======== + +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt700_evk/mimxrt798s/cm33_cpu0 + :goals: flash + +Open a serial terminal, reset the board (press the RESET button), and you should +see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS v3.7.0 *** + Hello World! mimxrt700_evk/mimxrt798s/cm33_cpu0 + +Debugging +========= + +Here is an example for the :zephyr:code-sample:`hello_world` application. This example uses the +:ref:`jlink-debug-host-tools` as default. + +.. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: mimxrt700_evk/mimxrt798s/cm33_cpu0 + :goals: debug + +Open a serial terminal, step through the application in your debugger, and you +should see the following message in the terminal: + +.. code-block:: console + + *** Booting Zephyr OS v3.7.0 *** + Hello World! mimxrt700_evk/mimxrt798s/cm33_cpu0 + +.. _i.MX RT700 Website: + https://www.nxp.com/products/processors-and-microcontrollers/arm-microcontrollers/i-mx-rt-crossover-mcus/i-mx-rt700-crossover-mcu-with-arm-cortex-m33-npu-dsp-and-gpu-cores:i.MX-RT700 diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi b/boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi new file mode 100644 index 00000000000000..a4f908954fdd56 --- /dev/null +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk-pinctrl.dtsi @@ -0,0 +1,36 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +&pinctrl { + pinmux_flexcomm0_lpuart: pinmux_flexcomm0_lpuart { + group0 { + pinmux = ; + input-enable; + slew-rate = "normal"; + drive-strength = "normal"; + }; + group1 { + pinmux = ; + slew-rate = "normal"; + drive-strength = "normal"; + }; + }; + + pinmux_flexcomm19_lpuart: pinmux_flexcomm19_lpuart { + group0 { + pinmux = ; + input-enable; + slew-rate = "normal"; + drive-strength = "normal"; + }; + group1 { + pinmux = ; + slew-rate = "normal"; + drive-strength = "normal"; + }; + }; +}; diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts new file mode 100644 index 00000000000000..d24a6888b272c3 --- /dev/null +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.dts @@ -0,0 +1,104 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "mimxrt700_evk-pinctrl.dtsi" + +/ { + model = "NXP MIMXRT700-EVK board"; + compatible = "nxp,mimxrt798s"; + + aliases { + led0 = &green_led; + led1 = &blue_led; + sw0 = &user_button_1; + sw1 = &user_button_2; + }; + + chosen { + zephyr,flash-controller = &mx25um51345g; + zephyr,flash = &mx25um51345g; + zephyr,sram = &sram0; + zephyr,console = &flexcomm0_lpuart0; + zephyr,shell-uart = &flexcomm0_lpuart0; + }; + + leds { + compatible = "gpio-leds"; + green_led: led_0 { + gpios = <&gpio0 18 GPIO_ACTIVE_HIGH>; + label = "User LED_GREEN"; + }; + blue_led: led_1 { + gpios = <&gpio0 17 GPIO_ACTIVE_HIGH>; + label = "User LED_BLUE"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_1: button_0 { + label = "User SW5"; + gpios = <&gpio0 9 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + user_button_2: button_1 { + label = "User SW7"; + gpios = <&gpio1 3 GPIO_ACTIVE_LOW>; + zephyr,code = ; + }; + }; +}; + +&systick { + status = "okay"; +}; + +&flexcomm0{ + status = "okay"; +}; + +&flexcomm0_lpuart0 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm0_lpuart>; + pinctrl-names = "default"; +}; + +&gpio0 { + status = "okay"; +}; + +&gpio1 { + status = "okay"; +}; + +&green_led { + status = "okay"; +}; + +&blue_led { + status = "okay"; +}; + +&xspi0 { + status = "okay"; + + mx25um51345g: mx25um51345g@0 { + compatible = "nxp,imx-xspi-mx25um51345g"; + /* MX25UM51245G is 64MB, 512MBit flash part */ + size = ; + reg = <0>; + spi-max-frequency = <200000000>; + status = "okay"; + jedec-id = [c2 81 3a]; + erase-block-size = <4096>; + write-block-size = <2>; /* FLASH_MCUX_FLEXSPI_MX25UM51345G_OPI_DTR set */ + }; +}; diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml new file mode 100644 index 00000000000000..9a8342ecfb50ed --- /dev/null +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0.yaml @@ -0,0 +1,20 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt700_evk/mimxrt798s/cm33_cpu0 +name: NXP MIMXRT700-EVK (CM33_CPU0) +type: mcu +arch: arm +ram: 512 +flash: 65536 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - uart +vendor: nxp diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0_defconfig b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0_defconfig new file mode 100644 index 00000000000000..9c7cb038062896 --- /dev/null +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu0_defconfig @@ -0,0 +1,18 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_BOARD_EARLY_INIT_HOOK=y + +# Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_SECURE=y diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts new file mode 100644 index 00000000000000..91a69dbf58b896 --- /dev/null +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.dts @@ -0,0 +1,66 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include +#include +#include "mimxrt700_evk-pinctrl.dtsi" + +/ { + model = "NXP MIMXRT700-EVK board"; + compatible = "nxp,mimxrt798s"; + + aliases { + led0 = &red_led; + sw0 = &user_button_1; + }; + + chosen { + zephyr,flash = &sram_code; + zephyr,sram = &sram0; + zephyr,console = &flexcomm19_lpuart19; + zephyr,shell-uart = &flexcomm19_lpuart19; + }; + + leds { + compatible = "gpio-leds"; + red_led: led_0 { + status = "okay"; + gpios = <&gpio8 6 GPIO_ACTIVE_HIGH>; + label = "User LED_RED"; + }; + }; + + gpio_keys { + compatible = "gpio-keys"; + user_button_1: button_0 { + label = "User SW6"; + gpios = <&gpio8 5 (GPIO_ACTIVE_LOW)>; + zephyr,code = ; + status = "okay"; + }; + }; +}; + +&systick { + status = "okay"; +}; + +&flexcomm19{ + status = "okay"; +}; + +&flexcomm19_lpuart19 { + status = "okay"; + current-speed = <115200>; + pinctrl-0 = <&pinmux_flexcomm19_lpuart>; + pinctrl-names = "default"; +}; + +&gpio8 { + status = "okay"; +}; diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml new file mode 100644 index 00000000000000..f3d4f5dccf42d6 --- /dev/null +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1.yaml @@ -0,0 +1,20 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +identifier: mimxrt700_evk/mimxrt798s/cm33_cpu1 +name: NXP MIMXRT700-EVK (CM33_CPU1) +type: mcu +arch: arm +ram: 256 +flash: 512 +toolchain: + - zephyr + - gnuarmemb + - xtools +supported: + - gpio + - uart +vendor: nxp diff --git a/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1_defconfig b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1_defconfig new file mode 100644 index 00000000000000..a7a0f73244a152 --- /dev/null +++ b/boards/nxp/mimxrt700_evk/mimxrt700_evk_mimxrt798s_cm33_cpu1_defconfig @@ -0,0 +1,19 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +CONFIG_CONSOLE=y +CONFIG_UART_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_GPIO=y + +CONFIG_ARM_MPU=y +CONFIG_HW_STACK_PROTECTION=y +CONFIG_BOARD_EARLY_INIT_HOOK=y + +# Enable TrustZone-M +CONFIG_TRUSTED_EXECUTION_SECURE=y +CONFIG_NXP_IMXRT_BOOT_HEADER=n diff --git a/doc/releases/migration-guide-4.1.rst b/doc/releases/migration-guide-4.1.rst index d35ab96073c736..2740e116a55a7c 100644 --- a/doc/releases/migration-guide-4.1.rst +++ b/doc/releases/migration-guide-4.1.rst @@ -39,6 +39,27 @@ LVGL Device Drivers and Devicetree ***************************** +* The :dtcompatible: ``nxp,lpc-iocon`` and ``nxp,rt-iocon-pinctrl`` driver won't be used + for RT 3 digital platforms. + New :dtcompatible:`nxp,iopctl` and :dtcompatible:`nxp,rt-iopctl-pinctrl` have been created + for iopctl IP on RT 3 digital platforms. Change iocon node to iopctl0 node on RT500/600 + platforms. New pinctrl model add instance index parameter in pin header files, however, + for the application layer, the pin macro name will not change. So it means application + layer won't be affected by changes in the driver layer.(:github:`81086`) + example: + + .. code-block:: devicetree + + / { + iopctl0: iopctl@4000 { + compatible = "nxp,iopctl"; + reg = <0x4000 0x1000>; + status = "okay"; + pinctrl: pinctrl { + compatible = "nxp,rt-iopctl-pinctrl"; + }; + }; + Controller Area Network (CAN) ============================= diff --git a/doc/releases/release-notes-4.0.rst b/doc/releases/release-notes-4.0.rst index afeddfeb6f42f2..41f259a1f8578b 100644 --- a/doc/releases/release-notes-4.0.rst +++ b/doc/releases/release-notes-4.0.rst @@ -13,6 +13,12 @@ Major enhancements with this release include: PSA Secure Storage API and of persistent keys in the PSA Crypto API on all board targets. It is now the standard way to provide device-specific protection to data at rest. (:github:`76222`) +* The introduction of the :ref:`comparator` device driver subsystem for analog + comparators, complete with shell support. It supports initial configuration through devicetree + and runtime configuration through vendor specific APIs. Initially the + :dtcompatible:`nordic,nrf-comp`, :dtcompatible:`nordic,nrf-lpcomp` and + :dtcompatible:`nxp,kinetis-acmp` are supported. + An overview of the changes required or recommended when migrating your application from Zephyr v3.7.0 to Zephyr v4.0.0 can be found in the separate :ref:`migration guide`. @@ -502,6 +508,12 @@ Drivers and Sensors * Hardware info +* Haptics + + * Introduced a haptics device driver subsystem selected with :kconfig:option:`CONFIG_HAPTICS` + * Added support for TI DRV2605 haptic driver IC (:dtcompatible:`ti,drv2605`) + * Added a sample for the DRV2605 haptic driver to trigger ROM events (:zephyr:code-sample:`drv2605`) + * I2C * Added initial support for Renesas RA8 I2C driver (:dtcompatible:`renesas,ra-iic`) @@ -717,6 +729,8 @@ Drivers and Sensors * USB * Added support for USB HS on STM32U59x/STM32U5Ax SoC variants. + * Enhanced DWC2 UDC driver + * Added UDC drivers for Smartbond, NuMaker USBD and RP2040 device controllers * Video @@ -724,16 +738,20 @@ Drivers and Sensors * Introduced API for partial frames transfer with the video buffer field ``line_offset`` * Introduced API for :ref:`multi-heap` video buffer allocation with :kconfig:option:`CONFIG_VIDEO_BUFFER_USE_SHARED_MULTI_HEAP` - * Introduced bindings for common video link properties in ``video-interfaces.yaml`` + * Introduced bindings for common video link properties in ``video-interfaces.yaml``. Migration to the + new bindings is tracked in :github:`80514` * Introduced missing :kconfig:option:`CONFIG_VIDEO_LOG_LEVEL` * Added a sample for capturing video and displaying it with LVGL (:zephyr:code-sample:`video-capture-to-lvgl`) + * Added an automatic test to check colorbar pattern correctness * Added support for GalaxyCore GC2145 image sensor (:dtcompatible:`gc,gc2145`) * Added support for ESP32-S3 LCD-CAM interface (:dtcompatible:`espressif,esp32-lcd-cam`) * Added support for NXP MCUX SMARTDMA interface (:dtcompatible:`nxp,smartdma`) * Added support for more OmniVision OV2640 controls (:dtcompatible:`ovti,ov2640`) * Added support for more OmniVision OV5640 controls (:dtcompatible:`ovti,ov5640`) * STM32: Implemented :c:func:`video_get_ctrl` and :c:func:`video_set_ctrl` APIs. + * Removed an init order circular dependency for the camera pipeline on NXP RT10xx platforms + (:github:`80304`) * W1 @@ -1017,6 +1035,13 @@ Networking USB *** +* New USB device stack: + + * Added USB CDC Network Control Model implementation + * Enhanced USB Audio class 2 implementation + * Made USB device stack high-bandwidth aware + * Enhanced CDC ACM and HID class implementations + Devicetree ********** diff --git a/drivers/clock_control/clock_control_mcux_syscon.c b/drivers/clock_control/clock_control_mcux_syscon.c index ca772e2cdd4594..99e0e218cb871c 100644 --- a/drivers/clock_control/clock_control_mcux_syscon.c +++ b/drivers/clock_control/clock_control_mcux_syscon.c @@ -25,7 +25,7 @@ static int mcux_lpc_syscon_clock_control_on(const struct device *dev, #endif /* defined(CONFIG_CAN_MCUX_MCAN) */ #if defined(CONFIG_COUNTER_NXP_MRT) if ((uint32_t)sub_system == MCUX_MRT_CLK) { -#if defined(CONFIG_SOC_FAMILY_LPC) || defined(CONFIG_SOC_SERIES_RW6XX) ||\ +#if defined(CONFIG_SOC_FAMILY_LPC) || defined(CONFIG_SOC_SERIES_RW6XX) || \ defined(CONFIG_SOC_SERIES_MCXN) CLOCK_EnableClock(kCLOCK_Mrt); #elif defined(CONFIG_SOC_FAMILY_NXP_IMXRT) @@ -236,14 +236,65 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de *rate = CLOCK_GetLPFlexCommClkFreq(9); break; + case MCUX_FLEXCOMM10_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(10); + break; + + case MCUX_FLEXCOMM11_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(11); + break; + + case MCUX_FLEXCOMM12_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(12); + break; + + case MCUX_FLEXCOMM13_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(13); + break; + + case MCUX_FLEXCOMM17_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(17); + break; + + case MCUX_FLEXCOMM18_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(18); + break; + + case MCUX_FLEXCOMM19_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(19); + break; + + case MCUX_FLEXCOMM20_CLK: + *rate = CLOCK_GetLPFlexCommClkFreq(20); + break; +#endif + + /* On RT7xx, flexcomm14 and 16 only can be LPSPI, flexcomm15 only can be I2C. */ +#if defined(CONFIG_SOC_SERIES_IMXRT7XX) && defined(CONFIG_SOC_FAMILY_NXP_IMXRT) + case MCUX_LPSPI14_CLK: + *rate = CLOCK_GetLPSpiClkFreq(14); + break; + case MCUX_LPI2C15_CLK: + *rate = CLOCK_GetLPI2cClkFreq(15); + break; + case MCUX_LPSPI16_CLK: + *rate = CLOCK_GetLPSpiClkFreq(16); + break; #endif #if (defined(FSL_FEATURE_SOC_USDHC_COUNT) && FSL_FEATURE_SOC_USDHC_COUNT) -#if CONFIG_SOC_SERIES_MCXN +#if defined(CONFIG_SOC_SERIES_MCXN) case MCUX_USDHC1_CLK: *rate = CLOCK_GetUsdhcClkFreq(); break; +#elif defined(CONFIG_SOC_SERIES_IMXRT7XX) + case MCUX_USDHC1_CLK: + *rate = CLOCK_GetUsdhcClkFreq(0); + break; + case MCUX_USDHC2_CLK: + *rate = CLOCK_GetUsdhcClkFreq(1); + break; #else case MCUX_USDHC1_CLK: *rate = CLOCK_GetSdioClkFreq(0); @@ -428,6 +479,18 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(const struct device *de *rate = CLOCK_GetLpuartClkFreq(4); break; #endif /* defined(CONFIG_UART_MCUX_LPUART) */ + +#if defined(CONFIG_DT_HAS_NXP_IMX_XSPI_ENABLED) + case MCUX_XSPI0_CLK: + *rate = CLOCK_GetXspiClkFreq(0); + break; + case MCUX_XSPI1_CLK: + *rate = CLOCK_GetXspiClkFreq(1); + break; + case MCUX_XSPI2_CLK: + *rate = CLOCK_GetXspiClkFreq(2); + break; +#endif /* defined(CONFIG_DT_HAS_NXP_IMX_XSPI_ENABLED) */ } return 0; diff --git a/drivers/gpio/gpio_mcux.c b/drivers/gpio/gpio_mcux.c index 34ef0bab910b6d..fcdeb0877c2344 100644 --- a/drivers/gpio/gpio_mcux.c +++ b/drivers/gpio/gpio_mcux.c @@ -17,12 +17,22 @@ #include +#if defined(CONFIG_PINCTRL_NXP_IOPCTL) +#include +#include +#include +#include +/* Use IOCON to configure electrical characteristic, set PORT_Type as void. */ +#define PORT_Type void +#endif + struct gpio_mcux_config { /* gpio_driver_config needs to be first */ struct gpio_driver_config common; GPIO_Type *gpio_base; PORT_Type *port_base; unsigned int flags; + uint32_t port_no; }; struct gpio_mcux_data { @@ -32,19 +42,23 @@ struct gpio_mcux_data { sys_slist_t callbacks; }; -static int gpio_mcux_configure(const struct device *dev, - gpio_pin_t pin, gpio_flags_t flags) +static int gpio_mcux_configure(const struct device *dev, gpio_pin_t pin, gpio_flags_t flags) { const struct gpio_mcux_config *config = dev->config; GPIO_Type *gpio_base = config->gpio_base; + +#if defined(CONFIG_PINCTRL_NXP_IOPCTL) + uint32_t port_no = config->port_no; + volatile uint32_t pinconfig = 0; +#else PORT_Type *port_base = config->port_base; uint32_t mask = 0U; uint32_t pcr = 0U; - /* Check for an invalid pin number */ if (pin >= ARRAY_SIZE(port_base->PCR)) { return -EINVAL; } +#endif if (((flags & GPIO_INPUT) != 0) && ((flags & GPIO_OUTPUT) != 0)) { return -ENOTSUP; @@ -64,6 +78,10 @@ static int gpio_mcux_configure(const struct device *dev, switch (flags & GPIO_DIR_MASK) { case GPIO_INPUT: gpio_base->PDDR &= ~BIT(pin); +#if defined(CONFIG_PINCTRL_NXP_IOPCTL) + /* Enable input buffer for input pins */ + pinconfig |= IOPCTL_INBUF_EN; +#endif break; case GPIO_OUTPUT: if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) { @@ -77,6 +95,36 @@ static int gpio_mcux_configure(const struct device *dev, return -ENOTSUP; } +#if defined(CONFIG_PINCTRL_NXP_IOPCTL) + /* Select GPIO mux for this pin (func 0 is always GPIO) */ + pinconfig |= IOPCTL_FUNC0; + + if ((flags & GPIO_PULL_UP) != 0) { + /* Enable and select pull up. */ + pinconfig |= (IOPCTL_PUPD_EN | IOPCTL_PULLUP_EN); + } else if ((flags & GPIO_PULL_DOWN) != 0) { + /* Enable and select pull down. */ + pinconfig |= (IOPCTL_PUPD_EN | IOPCTL_PULLDOWN_EN); + } + +#if defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH + /* Determine the drive strength */ + switch (flags & KINETIS_GPIO_DS_MASK) { + case KINETIS_GPIO_DS_DFLT: + /* Default is low drive strength */ + pinconfig |= IOPCTL_DRIVE_100OHM; + break; + case KINETIS_GPIO_DS_ALT: + /* Alternate is high drive strength */ + pinconfig |= IOPCTL_DRIVE_33OHM; + break; + default: + return -ENOTSUP; + } +#endif /* defined(FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH) && FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH */ + + IOPCTL_PinMuxSet(port_no, pin, pinconfig); +#else /* Set PCR mux to GPIO for the pin we are configuring */ mask |= PORT_PCR_MUX_MASK; pcr |= PORT_PCR_MUX(PORT_MUX_GPIO); @@ -84,7 +132,7 @@ static int gpio_mcux_configure(const struct device *dev, #if defined(FSL_FEATURE_PORT_HAS_INPUT_BUFFER) && FSL_FEATURE_PORT_HAS_INPUT_BUFFER /* Enable digital input buffer */ pcr |= PORT_PCR_IBE_MASK; -#endif +#endif /* defined(CONFIG_PINCTRL_NXP_IOPCTL) */ /* Now do the PORT module. Figure out the pullup/pulldown * configuration, but don't write it to the PCR register yet. @@ -121,6 +169,8 @@ static int gpio_mcux_configure(const struct device *dev, /* Accessing by pin, we only need to write one PCR register. */ port_base->PCR[pin] = (port_base->PCR[pin] & ~mask) | pcr; +#endif /* End of #if defined(CONFIG_PINCTRL_NXP_IOPCTL) */ + return 0; } @@ -134,9 +184,7 @@ static int gpio_mcux_port_get_raw(const struct device *dev, uint32_t *value) return 0; } -static int gpio_mcux_port_set_masked_raw(const struct device *dev, - uint32_t mask, - uint32_t value) +static int gpio_mcux_port_set_masked_raw(const struct device *dev, uint32_t mask, uint32_t value) { const struct gpio_mcux_config *config = dev->config; GPIO_Type *gpio_base = config->gpio_base; @@ -146,8 +194,7 @@ static int gpio_mcux_port_set_masked_raw(const struct device *dev, return 0; } -static int gpio_mcux_port_set_bits_raw(const struct device *dev, - uint32_t mask) +static int gpio_mcux_port_set_bits_raw(const struct device *dev, uint32_t mask) { const struct gpio_mcux_config *config = dev->config; GPIO_Type *gpio_base = config->gpio_base; @@ -157,8 +204,7 @@ static int gpio_mcux_port_set_bits_raw(const struct device *dev, return 0; } -static int gpio_mcux_port_clear_bits_raw(const struct device *dev, - uint32_t mask) +static int gpio_mcux_port_clear_bits_raw(const struct device *dev, uint32_t mask) { const struct gpio_mcux_config *config = dev->config; GPIO_Type *gpio_base = config->gpio_base; @@ -178,11 +224,10 @@ static int gpio_mcux_port_toggle_bits(const struct device *dev, uint32_t mask) return 0; } +#if !(defined(CONFIG_PINCTRL_NXP_IOPCTL)) #if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) -static uint32_t get_port_pcr_irqc_value_from_flags(const struct device *dev, - uint32_t pin, - enum gpio_int_mode mode, - enum gpio_int_trig trig) +static uint32_t get_port_pcr_irqc_value_from_flags(const struct device *dev, uint32_t pin, + enum gpio_int_mode mode, enum gpio_int_trig trig) { port_interrupt_t port_interrupt = 0; @@ -214,22 +259,21 @@ static uint32_t get_port_pcr_irqc_value_from_flags(const struct device *dev, return PORT_PCR_IRQC(port_interrupt); } -#endif /* !defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT */ +#endif /* !defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT */ +#endif /* !(defined(CONFIG_PINCTRL_NXP_IOPCTL)) */ #if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \ FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) -#define GPIO_MCUX_INTERRUPT_DISABLED 0 -#define GPIO_MCUX_INTERRUPT_LOGIC_0 0x8 -#define GPIO_MCUX_INTERRUPT_RISING_EDGE 0x9 -#define GPIO_MCUX_INTERRUPT_FALLING_EDGE 0xA -#define GPIO_MCUX_INTERRUPT_BOTH_EDGE 0xB -#define GPIO_MCUX_INTERRUPT_LOGIC_1 0xC - -static uint32_t get_gpio_icr_irqc_value_from_flags(const struct device *dev, - uint32_t pin, - enum gpio_int_mode mode, - enum gpio_int_trig trig) +#define GPIO_MCUX_INTERRUPT_DISABLED 0 +#define GPIO_MCUX_INTERRUPT_LOGIC_0 0x8 +#define GPIO_MCUX_INTERRUPT_RISING_EDGE 0x9 +#define GPIO_MCUX_INTERRUPT_FALLING_EDGE 0xA +#define GPIO_MCUX_INTERRUPT_BOTH_EDGE 0xB +#define GPIO_MCUX_INTERRUPT_LOGIC_1 0xC + +static uint32_t get_gpio_icr_irqc_value_from_flags(const struct device *dev, uint32_t pin, + enum gpio_int_mode mode, enum gpio_int_trig trig) { uint8_t gpio_interrupt = 0; @@ -261,49 +305,48 @@ static uint32_t get_gpio_icr_irqc_value_from_flags(const struct device *dev, return GPIO_ICR_IRQC(gpio_interrupt); } -#endif /* (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) */ +#endif /* (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) */ -static int gpio_mcux_pin_interrupt_configure(const struct device *dev, - gpio_pin_t pin, enum gpio_int_mode mode, - enum gpio_int_trig trig) +static int gpio_mcux_pin_interrupt_configure(const struct device *dev, gpio_pin_t pin, + enum gpio_int_mode mode, enum gpio_int_trig trig) { const struct gpio_mcux_config *config = dev->config; GPIO_Type *gpio_base = config->gpio_base; +#if !(defined(CONFIG_PINCTRL_NXP_IOPCTL)) PORT_Type *port_base = config->port_base; /* Check for an invalid pin number */ if (pin >= ARRAY_SIZE(port_base->PCR)) { return -EINVAL; } +#endif /* Check for an invalid pin configuration */ - if ((mode != GPIO_INT_MODE_DISABLED) && - ((gpio_base->PDDR & BIT(pin)) != 0)) { + if ((mode != GPIO_INT_MODE_DISABLED) && ((gpio_base->PDDR & BIT(pin)) != 0)) { return -EINVAL; } /* Check if GPIO port supports interrupts */ - if ((mode != GPIO_INT_MODE_DISABLED) && - ((config->flags & GPIO_INT_ENABLE) == 0U)) { + if ((mode != GPIO_INT_MODE_DISABLED) && ((config->flags & GPIO_INT_ENABLE) == 0U)) { return -ENOTSUP; } -#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) - uint32_t pcr = get_port_pcr_irqc_value_from_flags(dev, pin, mode, trig); - - port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr; -#elif (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \ +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \ FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) uint32_t icr = get_gpio_icr_irqc_value_from_flags(dev, pin, mode, trig); gpio_base->ICR[pin] = (gpio_base->ICR[pin] & ~GPIO_ICR_IRQC_MASK) | icr; -#endif /* !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) */ +#elif !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) + uint32_t pcr = get_port_pcr_irqc_value_from_flags(dev, pin, mode, trig); + + port_base->PCR[pin] = (port_base->PCR[pin] & ~PORT_PCR_IRQC_MASK) | pcr; +#endif /* !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) */ return 0; } -static int gpio_mcux_manage_callback(const struct device *dev, - struct gpio_callback *callback, bool set) +static int gpio_mcux_manage_callback(const struct device *dev, struct gpio_callback *callback, + bool set) { struct gpio_mcux_data *data = dev->data; @@ -316,21 +359,21 @@ static void gpio_mcux_port_isr(const struct device *dev) struct gpio_mcux_data *data = dev->data; uint32_t int_status; -#if !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) - int_status = config->port_base->ISFR; - - /* Clear the port interrupts */ - config->port_base->ISFR = int_status; -#elif (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \ +#if (defined(FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) && \ FSL_FEATURE_GPIO_HAS_INTERRUPT_CHANNEL_SELECT) int_status = config->gpio_base->ISFR[0]; /* Clear the gpio interrupts */ config->gpio_base->ISFR[0] = int_status; +#elif !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) && FSL_FEATURE_PORT_HAS_NO_INTERRUPT) + int_status = config->port_base->ISFR; + + /* Clear the port interrupts */ + config->port_base->ISFR = int_status; #else int_status = 0U; ARG_UNUSED(config); -#endif /* !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) */ +#endif /* !(defined(FSL_FEATURE_PORT_HAS_NO_INTERRUPT) */ gpio_fire_callbacks(&data->callbacks, dev, int_status); } @@ -350,20 +393,18 @@ static void gpio_mcux_shared_cluster_isr(const struct device *ports[]) #define CLUSTER_ARRAY_ELEMENT(node_id) DEVICE_DT_GET(node_id), -#define GPIO_MCUX_CLUSTER_INIT(node_id) \ - const struct device *shared_array##node_id[DT_CHILD_NUM_STATUS_OKAY(node_id) + 1] = \ - {DT_FOREACH_CHILD_STATUS_OKAY(node_id, CLUSTER_ARRAY_ELEMENT) NULL}; \ - \ - static int gpio_mcux_shared_interrupt_init##node_id(void) \ - { \ - IRQ_CONNECT(DT_IRQN(node_id), \ - DT_IRQ(node_id, priority), \ - gpio_mcux_shared_cluster_isr, \ - shared_array##node_id, 0); \ - irq_enable(DT_IRQN(node_id)); \ - \ - return 0; \ - } \ +#define GPIO_MCUX_CLUSTER_INIT(node_id) \ + const struct device *shared_array##node_id[DT_CHILD_NUM_STATUS_OKAY(node_id) + 1] = { \ + DT_FOREACH_CHILD_STATUS_OKAY(node_id, CLUSTER_ARRAY_ELEMENT) NULL}; \ + \ + static int gpio_mcux_shared_interrupt_init##node_id(void) \ + { \ + IRQ_CONNECT(DT_IRQN(node_id), DT_IRQ(node_id, priority), \ + gpio_mcux_shared_cluster_isr, shared_array##node_id, 0); \ + irq_enable(DT_IRQN(node_id)); \ + \ + return 0; \ + } \ SYS_INIT(gpio_mcux_shared_interrupt_init##node_id, POST_KERNEL, 0); DT_FOREACH_STATUS_OKAY(nxp_gpio_cluster, GPIO_MCUX_CLUSTER_INIT) @@ -404,47 +445,44 @@ static const struct gpio_driver_api gpio_mcux_driver_api = { #endif /* CONFIG_GPIO_GET_DIRECTION */ }; -#define GPIO_MCUX_IRQ_INIT(n) \ - do { \ - IRQ_CONNECT(DT_INST_IRQN(n), \ - DT_INST_IRQ(n, priority), \ - gpio_mcux_port_isr, \ - DEVICE_DT_INST_GET(n), 0); \ - \ - irq_enable(DT_INST_IRQN(n)); \ +#define GPIO_MCUX_IRQ_INIT(n) \ + do { \ + IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), gpio_mcux_port_isr, \ + DEVICE_DT_INST_GET(n), 0); \ + \ + irq_enable(DT_INST_IRQN(n)); \ } while (false) #define GPIO_PORT_BASE_ADDR(n) DT_REG_ADDR(DT_INST_PHANDLE(n, nxp_kinetis_port)) - -#define GPIO_DEVICE_INIT_MCUX(n) \ - static int gpio_mcux_port## n ## _init(const struct device *dev); \ - \ - static const struct gpio_mcux_config gpio_mcux_port## n ## _config = {\ - .common = { \ - .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\ - }, \ - .gpio_base = (GPIO_Type *) DT_INST_REG_ADDR(n), \ - .port_base = (PORT_Type *) GPIO_PORT_BASE_ADDR(n), \ - .flags = UTIL_AND(UTIL_OR(DT_INST_IRQ_HAS_IDX(n, 0), \ - GPIO_HAS_SHARED_IRQ), GPIO_INT_ENABLE), \ - }; \ - \ - static struct gpio_mcux_data gpio_mcux_port## n ##_data; \ - \ - DEVICE_DT_INST_DEFINE(n, \ - gpio_mcux_port## n ##_init, \ - NULL, \ - &gpio_mcux_port## n ##_data, \ - &gpio_mcux_port## n##_config, \ - POST_KERNEL, \ - CONFIG_GPIO_INIT_PRIORITY, \ - &gpio_mcux_driver_api); \ - \ - static int gpio_mcux_port## n ##_init(const struct device *dev) \ - { \ +#define GPIO_PORT_NUMBER(n) COND_CODE_1(DT_INST_NODE_HAS_PROP(n, gpio_port_offest), \ + (DT_INST_PROP(n, gpio_port_offest) + n), (n)) \ + +#define GPIO_DEVICE_INIT_MCUX(n) \ + static int gpio_mcux_port##n##_init(const struct device *dev); \ + \ + static const struct gpio_mcux_config gpio_mcux_port##n##_config = { \ + .common = \ + { \ + .port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n), \ + }, \ + .gpio_base = (GPIO_Type *)DT_INST_REG_ADDR(n), \ + .port_base = (PORT_Type *)GPIO_PORT_BASE_ADDR(n), \ + .flags = UTIL_AND(UTIL_OR(DT_INST_IRQ_HAS_IDX(n, 0), GPIO_HAS_SHARED_IRQ), \ + GPIO_INT_ENABLE), \ + .port_no = GPIO_PORT_NUMBER(n), \ + }; \ + \ + static struct gpio_mcux_data gpio_mcux_port##n##_data; \ + \ + DEVICE_DT_INST_DEFINE(n, gpio_mcux_port##n##_init, NULL, &gpio_mcux_port##n##_data, \ + &gpio_mcux_port##n##_config, POST_KERNEL, CONFIG_GPIO_INIT_PRIORITY, \ + &gpio_mcux_driver_api); \ + \ + static int gpio_mcux_port##n##_init(const struct device *dev) \ + { \ IF_ENABLED(DT_INST_IRQ_HAS_IDX(n, 0), \ - (GPIO_MCUX_IRQ_INIT(n);)) \ - return 0; \ + (GPIO_MCUX_IRQ_INIT(n);)) \ + return 0; \ } DT_INST_FOREACH_STATUS_OKAY(GPIO_DEVICE_INIT_MCUX) diff --git a/drivers/pinctrl/CMakeLists.txt b/drivers/pinctrl/CMakeLists.txt index 99cb8d6b9e5f97..30ce7286ce370e 100644 --- a/drivers/pinctrl/CMakeLists.txt +++ b/drivers/pinctrl/CMakeLists.txt @@ -20,6 +20,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX pinctrl_imx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOCON pinctrl_lpc_iocon.c) +zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOPCTL pinctrl_iopctl.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC13XX_CC26XX pinctrl_cc13xx_cc26xx.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_ESP32 pinctrl_esp32.c) zephyr_library_sources_ifdef(CONFIG_PINCTRL_RV32M1 pinctrl_rv32m1.c) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 511a8a22cb9ca2..25a32ec0342ca4 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -49,6 +49,7 @@ source "drivers/pinctrl/Kconfig.xec" source "drivers/pinctrl/Kconfig.imx" source "drivers/pinctrl/Kconfig.sifive" source "drivers/pinctrl/Kconfig.lpc_iocon" +source "drivers/pinctrl/Kconfig.iopctl" source "drivers/pinctrl/Kconfig.cc13xx_cc26xx" source "drivers/pinctrl/Kconfig.esp32" source "drivers/pinctrl/Kconfig.rv32m1" diff --git a/drivers/pinctrl/Kconfig.iopctl b/drivers/pinctrl/Kconfig.iopctl new file mode 100644 index 00000000000000..e057ab4e776461 --- /dev/null +++ b/drivers/pinctrl/Kconfig.iopctl @@ -0,0 +1,9 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config PINCTRL_NXP_IOPCTL + bool "IOPCTL Pin controller driver for NXP MCUs" + default y + depends on DT_HAS_NXP_RT_IOPCTL_PINCTRL_ENABLED + help + Enable pin controller driver for NXP MCUs diff --git a/drivers/pinctrl/Kconfig.lpc_iocon b/drivers/pinctrl/Kconfig.lpc_iocon index fdf101d93ebd32..9e8838ea5f9a5e 100644 --- a/drivers/pinctrl/Kconfig.lpc_iocon +++ b/drivers/pinctrl/Kconfig.lpc_iocon @@ -1,11 +1,10 @@ -# Copyright 2022, NXP +# Copyright 2022,2024 NXP # SPDX-License-Identifier: Apache-2.0 config PINCTRL_NXP_IOCON bool "IOCON Pin controller driver for NXP LPC MCUs" default y depends on DT_HAS_NXP_LPC_IOCON_PINCTRL_ENABLED || \ - DT_HAS_NXP_LPC11U6X_PINCTRL_ENABLED || \ - DT_HAS_NXP_RT_IOCON_PINCTRL_ENABLED + DT_HAS_NXP_LPC11U6X_PINCTRL_ENABLED help Enable pin controller driver for NXP LPC MCUs diff --git a/drivers/pinctrl/pinctrl_iopctl.c b/drivers/pinctrl/pinctrl_iopctl.c new file mode 100644 index 00000000000000..cdea81b5ce8091 --- /dev/null +++ b/drivers/pinctrl/pinctrl_iopctl.c @@ -0,0 +1,51 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#define DT_DRV_COMPAT nxp_iopctl + +#include +#include + +#define OFFSET(mux) (((mux) & 0xFFF00000) >> 20) +#define INDEX(mux) (((mux) & 0xF0000) >> 16) +#define Z_PINCTRL_IOPCTL_PIN_MASK 0xFFF + +/* IOPCTL register addresses. */ +static uint32_t *iopctl[] = { +#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(iopctl0))) + (uint32_t *)DT_REG_ADDR(DT_NODELABEL(iopctl0)), +#else + NULL, +#endif +#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(iopctl1))) + (uint32_t *)DT_REG_ADDR(DT_NODELABEL(iopctl1)), +#else + NULL, +#endif +#if (DT_NODE_HAS_STATUS_OKAY(DT_NODELABEL(iopctl2))) + (uint32_t *)DT_REG_ADDR(DT_NODELABEL(iopctl2)), +#else + NULL, +#endif +}; + +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) +{ + for (uint8_t i = 0; i < pin_cnt; i++) { + uint32_t pin_mux = pins[i]; + uint32_t index = INDEX(pin_mux); + uint32_t offset = OFFSET(pin_mux); + + if (index < ARRAY_SIZE(iopctl)) { + /* Set pinmux */ + *(iopctl[index] + offset) = (pin_mux & Z_PINCTRL_IOPCTL_PIN_MASK); + } else { + return -EINVAL; + } + } + + return 0; +} diff --git a/drivers/pinctrl/pinctrl_lpc_iocon.c b/drivers/pinctrl/pinctrl_lpc_iocon.c index 805cd46849ba0d..40ecc09d0997ba 100644 --- a/drivers/pinctrl/pinctrl_lpc_iocon.c +++ b/drivers/pinctrl/pinctrl_lpc_iocon.c @@ -1,5 +1,5 @@ /* - * Copyright 2022, NXP + * Copyright 2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -11,23 +11,40 @@ #include #endif +/* RT7xx requests to clear the reset bit in RESET module before a IOPCTL can be used. */ +#if defined(CONFIG_SOC_SERIES_IMXRT7XX) +#include + +/* For RT7xx , SDK driver need GPIO PORT NO and PIN NO for pin configuration purpose. */ +#define IOPCTL_PORT_NO_MASK 0xFF000000 +#define IOPCTL_PORT_NO_SHIFT 24 +#define IOPCTL_PIN_NO_MASK 0xFF0000 +#define IOPCTL_PIN_NO_SHIFT 16 +#define IOPCTL_MUX_MASK 0xFFFFUL +#define IOPCTL_MUX_SHIFT 0 + +#define PORT_NO(mux) (((mux) & IOPCTL_PORT_NO_MASK) >> IOPCTL_PORT_NO_SHIFT) +#define PIN_NO(mux) (((mux) & IOPCTL_PIN_NO_MASK) >> IOPCTL_PIN_NO_SHIFT) + +#else #define OFFSET(mux) (((mux) & 0xFFF00000) >> 20) +static volatile uint32_t *iocon = (volatile uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon)); #define TYPE(mux) (((mux) & 0xC0000) >> 18) #define IOCON_TYPE_D 0x0 #define IOCON_TYPE_I 0x1 #define IOCON_TYPE_A 0x2 +#endif -static volatile uint32_t *iocon = - (volatile uint32_t *)DT_REG_ADDR(DT_NODELABEL(iocon)); - -int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, - uintptr_t reg) +int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg) { for (uint8_t i = 0; i < pin_cnt; i++) { uint32_t pin_mux = pins[i]; +#if defined(CONFIG_SOC_SERIES_IMXRT7XX) + uint8_t port_no = PORT_NO(pin_mux); + uint8_t pin_no = PIN_NO(pin_mux); +#else uint32_t offset = OFFSET(pin_mux); - /* Check if this is an analog or i2c type pin */ switch (TYPE(pin_mux)) { case IOCON_TYPE_D: @@ -43,8 +60,22 @@ int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, /* Should not occur */ __ASSERT_NO_MSG(TYPE(pin_mux) <= IOCON_TYPE_A); } +#endif + /* Set pinmux */ +#if defined(CONFIG_SOC_SERIES_IMXRT7XX) + pin_mux &= IOPCTL_MUX_MASK; + /* PMIC_I2C_SDA/PMIC_I2C_SCL pin need to be configured separately */ + if ((port_no == 10) && (pin_no == 30)) { + IOPCTL1->PMIC_I2C_SDA = pin_mux; + } else if ((port_no == 10) && (pin_no == 31)) { + IOPCTL1->PMIC_I2C_SCL = pin_mux; + } else { + IOPCTL_PinMuxSet(port_no, pin_no, pin_mux); + } +#else *(iocon + offset) = pin_mux; +#endif } return 0; } diff --git a/drivers/serial/uart_gecko.c b/drivers/serial/uart_gecko.c index 11c396bcd9f1f4..32d3c71c910c15 100644 --- a/drivers/serial/uart_gecko.c +++ b/drivers/serial/uart_gecko.c @@ -492,13 +492,15 @@ static int uart_gecko_init(const struct device *dev) #ifdef CONFIG_PM_DEVICE static int uart_gecko_pm_action(const struct device *dev, enum pm_device_action action) { - const struct uart_gecko_config *config = dev->config; + __maybe_unused const struct uart_gecko_config *config = dev->config; switch (action) { case PM_DEVICE_ACTION_SUSPEND: +#ifdef USART_STATUS_TXIDLE /* Wait for TX FIFO to flush before suspending */ while (!(USART_StatusGet(config->base) & USART_STATUS_TXIDLE)) { } +#endif break; case PM_DEVICE_ACTION_RESUME: diff --git a/drivers/spi/Kconfig.ifx_cat1 b/drivers/spi/Kconfig.ifx_cat1 index d7dbbde1f7ef52..e08dc5e13ccc64 100644 --- a/drivers/spi/Kconfig.ifx_cat1 +++ b/drivers/spi/Kconfig.ifx_cat1 @@ -9,5 +9,6 @@ config SPI_INFINEON_CAT1 depends on DT_HAS_INFINEON_CAT1_SPI_ENABLED select USE_INFINEON_SPI select PINCTRL + select GPIO help This option enables the SPI driver for Infineon CAT1 family. diff --git a/drivers/wifi/infineon/Kconfig.airoc b/drivers/wifi/infineon/Kconfig.airoc index 319253378d3181..775396fb24579d 100644 --- a/drivers/wifi/infineon/Kconfig.airoc +++ b/drivers/wifi/infineon/Kconfig.airoc @@ -9,6 +9,7 @@ menuconfig WIFI_AIROC select NET_L2_WIFI_MGMT select SDIO_STACK select SDHC + select GPIO select WIFI_USE_NATIVE_NETWORKING select USE_INFINEON_ABSTRACTION_RTOS depends on DT_HAS_INFINEON_AIROC_WIFI_ENABLED diff --git a/dts/arm/nxp/nxp_rt5xx_common.dtsi b/dts/arm/nxp/nxp_rt5xx_common.dtsi index aa9db51f125520..31001f73f8ca3e 100644 --- a/dts/arm/nxp/nxp_rt5xx_common.dtsi +++ b/dts/arm/nxp/nxp_rt5xx_common.dtsi @@ -130,11 +130,12 @@ #clock-cells = <1>; }; - iocon: iocon@4000 { - compatible = "nxp,lpc-iocon"; + iopctl0: iopctl@4000 { + compatible = "nxp,iopctl"; reg = <0x4000 0x1000>; + status = "okay"; pinctrl: pinctrl { - compatible = "nxp,rt-iocon-pinctrl"; + compatible = "nxp,rt-iopctl-pinctrl"; }; }; diff --git a/dts/arm/nxp/nxp_rt6xx_common.dtsi b/dts/arm/nxp/nxp_rt6xx_common.dtsi index bf2dc2daccd910..c39c6847eb62b4 100644 --- a/dts/arm/nxp/nxp_rt6xx_common.dtsi +++ b/dts/arm/nxp/nxp_rt6xx_common.dtsi @@ -110,11 +110,12 @@ #clock-cells = <1>; }; - iocon: iocon@4000 { - compatible = "nxp,lpc-iocon"; + iopctl0: iopctl@4000 { + compatible = "nxp,iopctl"; reg = <0x4000 0x1000>; + status = "okay"; pinctrl: pinctrl { - compatible = "nxp,rt-iocon-pinctrl"; + compatible = "nxp,rt-iopctl-pinctrl"; }; }; diff --git a/dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi b/dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi new file mode 100644 index 00000000000000..f32d6b3ba6cd40 --- /dev/null +++ b/dts/arm/nxp/nxp_rt7xx_cm33_cpu0.dtsi @@ -0,0 +1,818 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-m33f"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + soc { + sram: sram@10000000 { + ranges = <0x0 0x10000000 0x780000 + 0x20000000 0x30000000 0x780000>; + }; + + peripheral: peripheral@50000000 { + ranges = <0x0 0x50000000 0x10000000>; + }; + + xspi0: spi@50184000 { + reg = <0x50184000 0x1000>, <0x38000000 DT_SIZE_M(128)>; + }; + + xspi1: spi@50185000 { + reg = <0x50185000 0x1000>, <0x18000000 DT_SIZE_M(128)>; + }; + + xspi2: spi@50411000 { + reg = <0x50411000 0x1000>, <0x70000000 DT_SIZE_M(128)>; + }; + + }; + + pinctrl: pinctrl { + compatible = "nxp,rt-iopctl-pinctrl"; + }; +}; + + +&sram { + #address-cells = <1>; + #size-cells = <1>; + + /* RT7XX SRAM partitions are shared between code and data. Boards can override + * the reg properties of either sram0 or sram_code nodes to change the balance + * of SRAM allocation. + * + * The SRAM region [0x000000-0x017FFF] is reserved for ROM bootloader execution. + * Can be reused after boot. + * The SRAM region [0x018000-0x17FFFF] is reserved for Non-cached shared memory + * or application data. + * The SRAM region [0x180000-0x1FFFFF] is reserved for CPU0 application, last + * 2MB non-cacheable data for NPU/GPU/Display etc. + * The SRAM region [0x200000-0x400000] is reserved for HiFi4 application. + */ + + sram4rom: memory@20000000{ + compatible = "mmio-sram"; + reg = <0x20000000 DT_SIZE_K(96)>; + }; + + /* This partition is shared with code in RAM */ + sram_shared_code: memory@20018000{ + compatible = "mmio-sram"; + reg = <0x20018000 DT_SIZE_K(1024+512-96)>; + }; + + sram0: memory@20180000 { + compatible = "mmio-sram"; + reg = <0x20180000 DT_SIZE_K(512)>; + }; + + sram1: memory@20200000 { + compatible = "zephyr,memory-region", "mmio-sram"; + reg = <0x20200000 DT_SIZE_K(2048)>; + zephyr,memory-region = "SRAM1"; + zephyr,memory-attr = ; + }; +}; + +&peripheral { + #address-cells = <1>; + #size-cells = <1>; + /* + * Note that the offsets here are relative to the base address. + * The base addresses differ between non-secure (0x40000000) + * and secure modes (0x50000000). + */ + + rstctl0: reset@0 { + compatible = "nxp,rstctl"; + reg = <0x0 0x1000>; + #reset-cells = <1>; + }; + + rstctl2: reset@67000 { + compatible = "nxp,rstctl"; + reg = <0x67000 0x1000>; + #reset-cells = <1>; + }; + + rstctl3: reset@60000 { + compatible = "nxp,rstctl"; + reg = <0x60000 0x1000>; + #reset-cells = <1>; + }; + + rstctl4: reset@a0000 { + compatible = "nxp,rstctl"; + reg = <0xa0000 0x1000>; + #reset-cells = <1>; + }; + + clkctl0: clkctl@1000 { + compatible = "nxp,lpc-syscon"; + reg = <0x1000 0x1000>; + #clock-cells = <1>; + }; + + clkctl2: clkctl@65000 { + compatible = "nxp,lpc-syscon"; + reg = <0x65000 0x1000>; + #clock-cells = <1>; + }; + + clkctl3: clkctl@61000 { + compatible = "nxp,lpc-syscon"; + reg = <0x61000 0x1000>; + #clock-cells = <1>; + }; + + clkctl4: clkctl@a1000 { + compatible = "nxp,lpc-syscon"; + reg = <0xa1000 0x1000>; + #clock-cells = <1>; + }; + + syscon0: syscon@2000 { + compatible = "nxp,lpc-syscon"; + reg = <0x2000 0x1000>; + #clock-cells = <1>; + }; + + syscon2: syscon@66000 { + compatible = "nxp,lpc-syscon"; + reg = <0x66000 0x1000>; + #clock-cells = <1>; + }; + + syscon3: syscon@62000 { + compatible = "nxp,lpc-syscon"; + reg = <0x62000 0x1000>; + #clock-cells = <1>; + }; + + syscon4: syscon@a2000 { + compatible = "nxp,lpc-syscon"; + reg = <0xa2000 0x1000>; + #clock-cells = <1>; + }; + + iopctl0: iopctl@4000 { + compatible = "nxp,iopctl"; + reg = <0x4000 0x1000>; + status = "okay"; + }; + + iopctl1: iopctl@64000 { + compatible = "nxp,iopctl"; + reg = <0x64000 0x1000>; + status = "okay"; + }; + + iopctl2: iopctl@a5000 { + compatible = "nxp,iopctl"; + reg = <0xa5000 0x1000>; + status = "okay"; + }; + + gpio0: gpio@100000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x100000 0x1000>; + interrupts = <91 0>,<92 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&gpio0>; + }; + + gpio1: gpio@102000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x102000 0x1000>; + interrupts = <93 0>,<94 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&gpio1>; + }; + + gpio2: gpio@104000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x104000 0x1000>; + interrupts = <95 0>,<96 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&gpio2>; + }; + + gpio3: gpio@106000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x106000 0x1000>; + interrupts = <97 0>,<98 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&gpio3>; + }; + + gpio4: gpio@108000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x108000 0x1000>; + interrupts = <99 0>,<100 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&gpio4>; + }; + + gpio5: gpio@10a000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x10a000 0x1000>; + interrupts = <101 0>,<102 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&gpio5>; + }; + + gpio6: gpio@10c000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x10c000 0x1000>; + interrupts = <103 0>,<104 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&gpio6>; + }; + + gpio7: gpio@10e000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x10e000 0x1000>; + interrupts = <105 0>,<106 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&gpio7>; + }; + + flexcomm0: flexcomm@110000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x110000 0x1000>; + interrupts = <7 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm0_lpuart0: uart@110000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x110000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM0_CLK>; + status = "disabled"; + }; + flexcomm0_lpspi0: lpspi@110000 { + compatible = "nxp,imx-lpspi"; + reg = <0x110000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM0_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm0_lpi2c0: lpi2c@110000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x110000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM0_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm1: flexcomm@111000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x111000 0x1000>; + interrupts = <8 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm1_lpuart1: uart@111000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x111000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM1_CLK>; + status = "disabled"; + }; + flexcomm1_lpspi1: lpspi@111000 { + compatible = "nxp,imx-lpspi"; + reg = <0x111000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM1_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm1_lpi2c1: lpi2c@111000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x111000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM1_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm2: flexcomm@112000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x112000 0x1000>; + interrupts = <9 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm2_lpuart2: uart@112000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x112000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM2_CLK>; + status = "disabled"; + }; + flexcomm2_lpspi2: lpspi@112000 { + compatible = "nxp,imx-lpspi"; + reg = <0x112000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM2_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm2_lpi2c2: lpi2c@112000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x112000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM2_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm3: flexcomm@113000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x113000 0x1000>; + interrupts = <10 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm3_lpuart3: uart@113000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x113000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM3_CLK>; + status = "disabled"; + }; + flexcomm3_lpspi3: lpspi@113000 { + compatible = "nxp,imx-lpspi"; + reg = <0x113000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM3_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm3_lpi2c3: lpi2c@113000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x113000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM3_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm4: flexcomm@171000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x171000 0x1000>; + interrupts = <11 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm4_lpuart4: uart@171000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x171000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM4_CLK>; + status = "disabled"; + }; + flexcomm4_lpspi4: lpspi@171000 { + compatible = "nxp,imx-lpspi"; + reg = <0x171000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM4_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm4_lpi2c4: lpi2c@171000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x171000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM4_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm5: flexcomm@172000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x172000 0x1000>; + interrupts = <12 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm5_lpuart5: uart@172000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x172000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM5_CLK>; + status = "disabled"; + }; + flexcomm5_lpspi5: lpspi@172000 { + compatible = "nxp,imx-lpspi"; + reg = <0x172000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM5_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm5_lpi2c5: lpi2c@172000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x172000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM5_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm6: flexcomm@173000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x173000 0x1000>; + interrupts = <35 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm6_lpuart6: uart@173000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x173000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM6_CLK>; + status = "disabled"; + }; + flexcomm6_lpspi6: lpspi@173000 { + compatible = "nxp,imx-lpspi"; + reg = <0x173000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM6_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm6_lpi2c6: lpi2c@173000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x173000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM6_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm7: flexcomm@174000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x174000 0x1000>; + interrupts = <36 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm7_lpuart7: uart@174000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x174000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM7_CLK>; + status = "disabled"; + }; + flexcomm7_lpspi7: lpspi@174000 { + compatible = "nxp,imx-lpspi"; + reg = <0x174000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM7_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm7_lpi2c7: lpi2c@174000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x174000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM7_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm8: flexcomm@199000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x199000 0x1000>; + interrupts = <47 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm8_lpuart8: uart@199000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x199000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM8_CLK>; + status = "disabled"; + }; + flexcomm8_lpspi8: lpspi@199000 { + compatible = "nxp,imx-lpspi"; + reg = <0x199000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM8_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm8_lpi2c8: lpi2c@199000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x199000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM8_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm9: flexcomm@19a000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x19a000 0x1000>; + interrupts = <48 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm9_lpuart9: uart@19a000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x19a000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM9_CLK>; + status = "disabled"; + }; + flexcomm9_lpspi9: lpspi@19a000 { + compatible = "nxp,imx-lpspi"; + reg = <0x19a000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM9_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm9_lpi2c9: lpi2c@19a000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x19a000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM9_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm10: flexcomm@19b000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x19b000 0x1000>; + interrupts = <49 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm10_lpuart10: uart@19b000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x19b000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM10_CLK>; + status = "disabled"; + }; + flexcomm10_lpspi10: lpspi@19b000 { + compatible = "nxp,imx-lpspi"; + reg = <0x19b000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM10_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm10_lpi2c10: lpi2c@19b000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x19b000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM10_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm11: flexcomm@19c000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x19c000 0x1000>; + interrupts = <50 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm11_lpuart11: uart@19c000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x19c000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM11_CLK>; + status = "disabled"; + }; + flexcomm11_lpspi11: lpspi@19c000 { + compatible = "nxp,imx-lpspi"; + reg = <0x19c000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM11_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm11_lpi2c11: lpi2c@19c000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x19c000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM11_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm12: flexcomm@19d000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x19d000 0x1000>; + interrupts = <51 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm12_lpuart12: uart@19d000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x19d000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM12_CLK>; + status = "disabled"; + }; + flexcomm12_lpspi12: lpspi@19d000 { + compatible = "nxp,imx-lpspi"; + reg = <0x19d000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM12_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm12_lpi2c12: lpi2c@19d000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x19d000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM12_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm13: flexcomm@19e000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x19e000 0x1000>; + interrupts = <52 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm13_lpuart13: uart@19e000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x19e000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM13_CLK>; + status = "disabled"; + }; + flexcomm13_lpspi13: lpspi@19e000 { + compatible = "nxp,imx-lpspi"; + reg = <0x19e000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM13_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm13_lpi2c13: lpi2c@19e000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x19e000 0x1000>; + clocks = <&clkctl0 MCUX_FLEXCOMM13_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + /* LPFlexcomm14/16 only support LPSPI function */ + lpspi14: spi@484000 { + compatible = "nxp,imx-lpspi"; + reg = <0x484000 0x1000>; + interrupts = <13 0>; + clocks = <&clkctl4 MCUX_LPSPI14_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + + /* LPFlexcomm15 only support LPI2C function. */ + lpi2c15: i2c@213000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x213000 0x1000>; + interrupts = <14 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkctl4 MCUX_LPI2C15_CLK>; + status = "disabled"; + }; + + /* LPFlexcomm14/16 only support LPSPI function */ + lpspi16: spi@405000 { + compatible = "nxp,imx-lpspi"; + reg = <0x405000 0x1000>; + interrupts = <53 0>; + clocks = <&clkctl4 MCUX_LPSPI16_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; +}; + +&xspi0 { + compatible = "nxp,imx-xspi"; + status = "disabled"; + interrupts = <42 0>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&clkctl0 MCUX_XSPI_CLK>; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi b/dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi new file mode 100644 index 00000000000000..341ac046fa58ec --- /dev/null +++ b/dts/arm/nxp/nxp_rt7xx_cm33_cpu1.dtsi @@ -0,0 +1,353 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include +#include +#include +#include +#include + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu1: cpu@0 { + compatible = "arm,cortex-m33f"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mpu: mpu@e000ed90 { + compatible = "arm,armv8m-mpu"; + reg = <0xe000ed90 0x40>; + }; + }; + }; + + soc { + sram: sram@10000000 { + ranges = <0x0 0x10000000 0x780000 + 0x20000000 0x30000000 0x780000>; + }; + + peripheral: peripheral@50000000 { + ranges = <0x0 0x50000000 0x10000000>; + }; + + xspi2: spi@50411000 { + reg = <0x50411000 0x1000>, <0x70000000 DT_SIZE_M(128)>; + }; + + }; + + pinctrl: pinctrl { + compatible = "nxp,rt-iopctl-pinctrl"; + }; +}; + +&sram { + #address-cells = <1>; + #size-cells = <1>; + + /* RT7XX SRAM partitions are shared between code and data. Boards can + * override the reg properties of either sram0 or sram_code nodes to + * change the balance of SRAM allocation. + * + * The SRAM region [0x580000-0x5BFFFF] is reserved for shared memory or application data. + * The SRAM region [0x5C0000-0x67FFFF] is reserved for CPU1 application. + * The SRAM region [0x680000-0x77FFFF] is reserved for HiFi1 application. + */ + + sram_code: memory@600000{ + compatible = "mmio-sram"; + reg = <0x600000 DT_SIZE_K(512)>; + }; + + /* This partition is shared with code in RAM */ + sram_shared_code: memory@20058000{ + compatible = "mmio-sram"; + reg = <0x20058000 DT_SIZE_K(256)>; + }; + + sram0: memory@205C0000 { + compatible = "mmio-sram"; + /* Only use 256K, align with SDK */ + reg = <0x205C0000 DT_SIZE_K(256)>; + }; +}; + +&peripheral { + #address-cells = <1>; + #size-cells = <1>; + /* + * Note that the offsets here are relative to the base address. + * The base addresses differ between non-secure (0x40000000) + * and secure modes (0x50000000). + */ + + rstctl1: reset@40000 { + compatible = "nxp,rstctl"; + reg = <0x40000 0x1000>; + #reset-cells = <1>; + }; + + rstctl2: reset@67000 { + compatible = "nxp,rstctl"; + reg = <0x67000 0x1000>; + #reset-cells = <1>; + }; + + rstctl3: reset@60000 { + compatible = "nxp,rstctl"; + reg = <0x60000 0x1000>; + #reset-cells = <1>; + }; + + rstctl4: reset@a0000 { + compatible = "nxp,rstctl"; + reg = <0xa0000 0x1000>; + #reset-cells = <1>; + }; + + clkctl1: clkctl@41000 { + compatible = "nxp,lpc-syscon"; + reg = <0x41000 0x1000>; + #clock-cells = <1>; + }; + + clkctl2: clkctl@65000 { + compatible = "nxp,lpc-syscon"; + reg = <0x65000 0x1000>; + #clock-cells = <1>; + }; + + clkctl3: clkctl@61000 { + compatible = "nxp,lpc-syscon"; + reg = <0x61000 0x1000>; + #clock-cells = <1>; + }; + + clkctl4: clkctl@a1000 { + compatible = "nxp,lpc-syscon"; + reg = <0xa1000 0x1000>; + #clock-cells = <1>; + }; + + syscon1: syscon@42000 { + compatible = "nxp,lpc-syscon"; + reg = <0x42000 0x1000>; + #clock-cells = <1>; + }; + + syscon2: syscon@66000 { + compatible = "nxp,lpc-syscon"; + reg = <0x66000 0x1000>; + #clock-cells = <1>; + }; + + syscon3: syscon@62000 { + compatible = "nxp,lpc-syscon"; + reg = <0x62000 0x1000>; + #clock-cells = <1>; + }; + + syscon4: syscon@a2000 { + compatible = "nxp,lpc-syscon"; + reg = <0xa2000 0x1000>; + #clock-cells = <1>; + }; + + iopctl1: iopctl@64000 { + compatible = "nxp,iopctl"; + reg = <0x64000 0x1000>; + status = "okay"; + }; + + iopctl2: iopctl@a5000 { + compatible = "nxp,iopctl"; + reg = <0xa5000 0x1000>; + status = "okay"; + }; + + gpio8: gpio@320000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x320000 0x1000>; + interrupts = <61 0>,<62 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&gpio8>; + gpio-port-offest = <8>; + }; + + gpio9: gpio@322000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x322000 0x1000>; + interrupts = <63 0>,<64 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&gpio9>; + gpio-port-offest = <8>; + }; + + gpio10: gpio@324000 { + compatible = "nxp,kinetis-gpio"; + status = "disabled"; + reg = <0x324000 0x1000>; + interrupts = <65 0>,<66 0>; + gpio-controller; + #gpio-cells = <2>; + nxp,kinetis-port = <&gpio10>; + gpio-port-offest = <8>; + }; + + flexcomm17: flexcomm@326000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x326000 0x1000>; + interrupts = <11 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm17_lpuart17: uart@326000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x326000 0x1000>; + clocks = <&clkctl1 MCUX_FLEXCOMM17_CLK>; + status = "disabled"; + }; + flexcomm17_lpspi17: lpspi@326000 { + compatible = "nxp,imx-lpspi"; + reg = <0x326000 0x1000>; + clocks = <&clkctl1 MCUX_FLEXCOMM17_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm17_lpi2c17: lpi2c@326000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x326000 0x1000>; + clocks = <&clkctl1 MCUX_FLEXCOMM17_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm18: flexcomm@327000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x327000 0x1000>; + interrupts = <12 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm18_lpuart18: uart@327000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x327000 0x1000>; + clocks = <&clkctl1 MCUX_FLEXCOMM18_CLK>; + status = "disabled"; + }; + flexcomm18_lpspi18: lpspi@327000 { + compatible = "nxp,imx-lpspi"; + reg = <0x327000 0x1000>; + clocks = <&clkctl1 MCUX_FLEXCOMM18_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm18_lpi2c18: lpi2c@327000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x327000 0x1000>; + clocks = <&clkctl1 MCUX_FLEXCOMM18_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm19: flexcomm@328000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x328000 0x1000>; + interrupts = <13 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm19_lpuart19: uart@328000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x328000 0x1000>; + clocks = <&clkctl1 MCUX_FLEXCOMM19_CLK>; + status = "disabled"; + }; + flexcomm19_lpspi19: lpspi@328000 { + compatible = "nxp,imx-lpspi"; + reg = <0x328000 0x1000>; + clocks = <&clkctl1 MCUX_FLEXCOMM19_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm19_lpi2c19: lpi2c@328000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x328000 0x1000>; + clocks = <&clkctl1 MCUX_FLEXCOMM19_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + + flexcomm20: flexcomm@329000 { + compatible = "nxp,lp-flexcomm"; + reg = <0x329000 0x1000>; + interrupts = <14 0>; + status = "disabled"; + + /* Empty ranges property implies parent and child address space is identical */ + ranges = <>; + #address-cells = <1>; + #size-cells = <1>; + + flexcomm20_lpuart20: uart@329000 { + compatible = "nxp,kinetis-lpuart"; + reg = <0x329000 0x1000>; + clocks = <&clkctl1 MCUX_FLEXCOMM20_CLK>; + status = "disabled"; + }; + flexcomm20_lpspi20: lpspi@329000 { + compatible = "nxp,imx-lpspi"; + reg = <0x329000 0x1000>; + clocks = <&clkctl1 MCUX_FLEXCOMM20_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + flexcomm20_lpi2c20: lpi2c@329000 { + compatible = "nxp,imx-lpi2c"; + reg = <0x329000 0x1000>; + clocks = <&clkctl1 MCUX_FLEXCOMM20_CLK>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; +}; + +&nvic { + arm,num-irq-priority-bits = <3>; +}; diff --git a/dts/bindings/gpio/nxp,kinetis-gpio.yaml b/dts/bindings/gpio/nxp,kinetis-gpio.yaml index 845a13714e0d85..1ee1c8db0ddf37 100644 --- a/dts/bindings/gpio/nxp,kinetis-gpio.yaml +++ b/dts/bindings/gpio/nxp,kinetis-gpio.yaml @@ -18,6 +18,12 @@ properties: A phandle reference to the device tree node that contains the pinmux port associated with this GPIO controller. + gpio-port-offest: + type: int + default: 0 + description: | + Describes an offset between inst index and actual GPIO port number. + gpio-cells: - pin - flags diff --git a/dts/bindings/mtd/nxp,imx-xspi-device.yaml b/dts/bindings/mtd/nxp,imx-xspi-device.yaml new file mode 100644 index 00000000000000..d067b878c93064 --- /dev/null +++ b/dts/bindings/mtd/nxp,imx-xspi-device.yaml @@ -0,0 +1,6 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: NXP XSPI device + +include: [spi-device.yaml, "jedec,jesd216.yaml"] diff --git a/dts/bindings/mtd/nxp,imx-xspi-mx25um51345g.yaml b/dts/bindings/mtd/nxp,imx-xspi-mx25um51345g.yaml new file mode 100644 index 00000000000000..3f2fd8e66ee748 --- /dev/null +++ b/dts/bindings/mtd/nxp,imx-xspi-mx25um51345g.yaml @@ -0,0 +1,8 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: NXP XSPI MX25UM51345G + +compatible: "nxp,imx-xspi-mx25um51345g" + +include: ["nxp,imx-xspi-device.yaml", soc-nv-flash.yaml] diff --git a/dts/bindings/pinctrl/nxp,iopctl.yaml b/dts/bindings/pinctrl/nxp,iopctl.yaml new file mode 100644 index 00000000000000..72289cc23a5deb --- /dev/null +++ b/dts/bindings/pinctrl/nxp,iopctl.yaml @@ -0,0 +1,12 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: IO PAD Controller (IOPCTL) + +compatible: "nxp,iopctl" + +include: base.yaml + +properties: + reg: + required: true diff --git a/dts/bindings/pinctrl/nxp,rt-iocon-pinctrl.yaml b/dts/bindings/pinctrl/nxp,rt-iopctl-pinctrl.yaml similarity index 76% rename from dts/bindings/pinctrl/nxp,rt-iocon-pinctrl.yaml rename to dts/bindings/pinctrl/nxp,rt-iopctl-pinctrl.yaml index e98eeaea420708..e87d5ec9b62ea2 100644 --- a/dts/bindings/pinctrl/nxp,rt-iocon-pinctrl.yaml +++ b/dts/bindings/pinctrl/nxp,rt-iopctl-pinctrl.yaml @@ -1,8 +1,8 @@ -# Copyright 2022, NXP +# Copyright 2022,2024 NXP # SPDX-License-Identifier: Apache-2.0 description: | - RT600/RT500 pin control node. This node defines pin configurations in pin + RT700/RT600/RT500 pin control node. This node defines pin configurations in pin groups, and has the 'pinctrl' node identifier in the SOC's devicetree. Each group within the pin configuration defines a peripheral's pin configuration. Each numbered subgroup represents pins with shared configuration for that @@ -21,31 +21,31 @@ description: | If only the required properties are supplied, the ICON_PIO register will be assigned the following values: - IOCON_FUNC=, - IOCON_PUPDENA = 0, - IOCON_PUPDSEL = 0, - IOCON_IBENA = 0, - IOCON_SLEWRATE = , - IOCON_FULLDRIVE = , - IOCON_AMENA = 0, - IOCON_ODENA = 0, - IOCON_IIENA = 0, + IOPCTL_FUNC=, + IOPCTL_PUPDENA = 0, + IOPCTL_PUPDSEL = 0, + IOPCTL_IBENA = 0, + IOPCTL_SLEWRATE = , + IOPCTL_FULLDRIVE = , + IOPCTL_AMENA = 0, + IOPCTL_ODENA = 0, + IOPCTL_IIENA = 0, Note the inherited pinctrl properties defined below have the following effects: - drive-open-drain: IOCON_ODENA=1 - bias-pull-up: IOCON_PUPDENA=1, IOCON_PUPSEL=1 - bias-pull-down: IOCON_PUPDENA=1, IOCON_PUPSEL=0 - input-enable: IOCON_IBENA=1 + drive-open-drain: IOPCTL_ODENA=1 + bias-pull-up: IOPCTL_PUPDENA=1, IOPCTL_PUPSEL=1 + bias-pull-down: IOPCTL_PUPDENA=1, IOPCTL_PUPSEL=0 + input-enable: IOPCTL_IBENA=1 -compatible: "nxp,rt-iocon-pinctrl" +compatible: "nxp,rt-iopctl-pinctrl" include: base.yaml child-binding: - description: iMX RT IOCON pin controller pin group + description: iMX RT IOPCTL pin controller pin group child-binding: description: | - iMX RT IOCON pin controller pin configuration node + iMX RT IOPCTL pin controller pin configuration node include: - name: pincfg-node.yaml @@ -69,7 +69,7 @@ child-binding: - "normal" - "slow" description: | - Pin output slew rate. Sets the SLEWRATE field in the IOCON register. + Pin output slew rate. Sets the SLEWRATE field in the IOPCTL register. 0 SLEWRATE_0- normal mode, output slew rate is standard 1 SLEWRATE_1- slow mode, output slew rate is slower drive-strength: @@ -80,7 +80,7 @@ child-binding: - "high" description: | Pin output drive strength. Sets the FULLDRIVE field in the - IOCON register. + IOPCTL register. 0 FULLDRIVE_0- Normal output drive mode 1 FULLDRIVE_1- Full output drive mode, output strength is twice the drive strength of normal drive mode. diff --git a/dts/bindings/spi/nxp,imx-xspi.yaml b/dts/bindings/spi/nxp,imx-xspi.yaml new file mode 100644 index 00000000000000..43d222a4db4d6b --- /dev/null +++ b/dts/bindings/spi/nxp,imx-xspi.yaml @@ -0,0 +1,20 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +description: NXP XSPI controller + +compatible: "nxp,imx-xspi" + +include: [spi-controller.yaml, pinctrl-device.yaml] + +properties: + reg: + required: true + + interrupts: + required: true + +child-binding: + description: NXP XSPI port + + include: nxp,imx-xspi-device.yaml diff --git a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h index c26735174880b9..822cdd62012864 100644 --- a/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h +++ b/include/zephyr/dt-bindings/clock/mcux_lpc_syscon_clock.h @@ -40,9 +40,16 @@ #define MCUX_FLEXCOMM14_CLK MCUX_HS_SPI_CLK #define MCUX_PMIC_I2C_CLK MCUX_LPC_CLK_ID(0x01, 0x0F) #define MCUX_HS_SPI1_CLK MCUX_LPC_CLK_ID(0x01, 0x10) - -#define MCUX_USDHC1_CLK MCUX_LPC_CLK_ID(0x02, 0x00) -#define MCUX_USDHC2_CLK MCUX_LPC_CLK_ID(0x02, 0x01) +#define MCUX_FLEXCOMM17_CLK MCUX_LPC_CLK_ID(0x01, 0x11) +#define MCUX_FLEXCOMM18_CLK MCUX_LPC_CLK_ID(0x01, 0x12) +#define MCUX_FLEXCOMM19_CLK MCUX_LPC_CLK_ID(0x01, 0x13) +#define MCUX_FLEXCOMM20_CLK MCUX_LPC_CLK_ID(0x01, 0x14) +/* On RT7xx, flexcomm14 and 16 only can be LPSPI, flexcomm15 only can be I2C. */ +#define MCUX_LPSPI14_CLK MCUX_LPC_CLK_ID(0x01, 0x24) +#define MCUX_LPI2C15_CLK MCUX_LPC_CLK_ID(0x01, 0x25) +#define MCUX_LPSPI16_CLK MCUX_LPC_CLK_ID(0x01, 0x26) +#define MCUX_USDHC1_CLK MCUX_LPC_CLK_ID(0x02, 0x00) +#define MCUX_USDHC2_CLK MCUX_LPC_CLK_ID(0x02, 0x01) #define MCUX_MCAN_CLK MCUX_LPC_CLK_ID(0x03, 0x00) @@ -98,4 +105,8 @@ #define MCUX_LPUART3_CLK MCUX_LPC_CLK_ID(0x13, 0x03) #define MCUX_LPUART4_CLK MCUX_LPC_CLK_ID(0x13, 0x04) +#define MCUX_XSPI_CLK MCUX_LPC_CLK_ID(0x14, 0x00) +#define MCUX_XSPI0_CLK MCUX_LPC_CLK_ID(0x14, 0x00) +#define MCUX_XSPI1_CLK MCUX_LPC_CLK_ID(0x14, 0x01) +#define MCUX_XSPI2_CLK MCUX_LPC_CLK_ID(0x14, 0x02) #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_MCUX_LPC_SYSCON_H_ */ diff --git a/modules/Kconfig.mcux b/modules/Kconfig.mcux index 87489810741adf..ee15557d590839 100644 --- a/modules/Kconfig.mcux +++ b/modules/Kconfig.mcux @@ -394,4 +394,9 @@ config NXP_RF_IMU help RF_IMU adapter is needed for intercore messaging. +config HAS_GLIKEY + bool + help + Set if the GLIKEY module is present in the SoC. + endif # HAS_MCUX diff --git a/soc/mediatek/mtk_adsp/mt8195_adsp/linker.ld b/soc/mediatek/mtk_adsp/mt8195_adsp/linker.ld index 37e11375c3b4f7..b58b91e5dc97f8 100644 --- a/soc/mediatek/mtk_adsp/mt8195_adsp/linker.ld +++ b/soc/mediatek/mtk_adsp/mt8195_adsp/linker.ld @@ -136,4 +136,7 @@ SECTIONS { */ #include +#ifdef CONFIG_LLEXT +#include +#endif } /* SECTIONS */ diff --git a/soc/nxp/common/Kconfig.xspi_xip b/soc/nxp/common/Kconfig.xspi_xip new file mode 100644 index 00000000000000..ab075efcfc18ef --- /dev/null +++ b/soc/nxp/common/Kconfig.xspi_xip @@ -0,0 +1,42 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +DT_CHOSEN_Z_FLASH := zephyr,flash +DT_COMPAT_XSPI := nxp,imx-xspi + +DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH)) +DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE)) + +DT_FLASH_PARENT_IS_XSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_XSPI)) +DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size) + +config FLASH_BASE_ADDRESS + default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \ + if $(DT_FLASH_PARENT_IS_XSPI) + default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) + +config FLASH_SIZE + default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) + +config FLASH_MCUX_XSPI_XIP + bool + default $(DT_FLASH_PARENT_IS_XSPI) + select XIP + help + Allows the soc to safely initialize the clocks for the + XSpi when planning to execute code in XSpi Memory. + +if FLASH_MCUX_XSPI_XIP + +config CODE_DATA_RELOCATION_SRAM + default y + +config FLASH_MCUX_XSPI_XIP_MEM + string + prompt "Xspi drivers memory location" + default "RAM" + help + Select the location to run the XSPI drivers when using + the flash API. + +endif diff --git a/soc/nxp/imxrt/CMakeLists.txt b/soc/nxp/imxrt/CMakeLists.txt index ac5302a32fc7ea..82d23ee5b5a0de 100644 --- a/soc/nxp/imxrt/CMakeLists.txt +++ b/soc/nxp/imxrt/CMakeLists.txt @@ -66,7 +66,7 @@ if(CONFIG_SOC_SERIES_IMXRT118X) zephyr_compile_definitions(XIP_EXTERNAL_FLASH) endif() -if(CONFIG_SOC_SERIES_IMXRT6XX OR CONFIG_SOC_SERIES_IMXRT5XX) +if(CONFIG_SOC_SERIES_IMXRT6XX OR CONFIG_SOC_SERIES_IMXRT5XX OR CONFIG_SOC_SERIES_IMXRT7XX) zephyr_linker_sources_ifdef(CONFIG_USB_DEVICE_DRIVER SECTIONS usb.ld) zephyr_linker_sources_ifdef(CONFIG_UDC_DRIVER SECTIONS usb.ld) endif() diff --git a/soc/nxp/imxrt/Kconfig b/soc/nxp/imxrt/Kconfig index eb10a3a1a7602d..4d1c8aea227b29 100644 --- a/soc/nxp/imxrt/Kconfig +++ b/soc/nxp/imxrt/Kconfig @@ -10,7 +10,13 @@ if SOC_FAMILY_NXP_IMXRT # can override the defaults given here rsource "*/Kconfig" +if DT_HAS_NXP_IMX_FLEXSPI_ENABLED rsource "../common/Kconfig.flexspi_xip" +endif + +if DT_HAS_NXP_IMX_XSPI_ENABLED +rsource "../common/Kconfig.xspi_xip" +endif # Note- When SECOND_CORE_MCUX is set, the dependencies for this Kconfig # should be set elsewhere, since the determination of which SOC core @@ -29,8 +35,13 @@ rsource "../common/Kconfig.rom_loader" choice BOOT_DEVICE prompt "Boot device" + default BOOT_XSPI_NOR if DT_HAS_NXP_IMX_XSPI_ENABLED default BOOT_FLEXSPI_NOR +config BOOT_XSPI_NOR + bool "XPI serial NOR" + depends on DT_HAS_NXP_IMX_XSPI_ENABLED + config BOOT_FLEXSPI_NOR bool "FlexSPI serial NOR" depends on HAS_MCUX_FLEXSPI @@ -49,6 +60,8 @@ config BOOT_SEMC_NAND endchoice # BOOT_DEVICE +if BOOT_FLEXSPI_NOR + config FLEXSPI_CONFIG_BLOCK_OFFSET hex "FlexSPI config block offset" default 0x0 if BOOT_FLEXSPI_NOR @@ -59,6 +72,21 @@ config FLEXSPI_CONFIG_BLOCK_OFFSET sequence (optional), etc. The boot ROM expects FlexSPI configuration parameter to be presented in serial nor flash. +endif # BOOT_FLEXSPI_NOR + +if BOOT_XSPI_NOR + +config XSPI_CONFIG_BLOCK_OFFSET + hex "XSPI config block offset" + default 0x0 + help + XSPI configuration block consists of parameters regarding specific + flash devices including read command sequence, quad mode enablement + sequence (optional), etc. The boot ROM expects XSPI configuration + parameter to be presented in serial nor flash. + +endif # BOOT_XSPI_NOR + config IMAGE_VECTOR_TABLE_OFFSET hex "Image vector table offset" default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR diff --git a/soc/nxp/imxrt/boot_header.ld b/soc/nxp/imxrt/boot_header.ld index 618c760f0170b2..b61487c481955b 100644 --- a/soc/nxp/imxrt/boot_header.ld +++ b/soc/nxp/imxrt/boot_header.ld @@ -9,11 +9,15 @@ __VECTOR_TABLE = CONFIG_ROM_START_OFFSET; __Vectors = __VECTOR_TABLE; #endif +#if defined(CONFIG_BOOT_XSPI_NOR) +. = CONFIG_XSPI_CONFIG_BLOCK_OFFSET; +#else . = CONFIG_FLEXSPI_CONFIG_BLOCK_OFFSET; +#endif #if defined(CONFIG_SOC_SERIES_IMXRT11XX) || defined(CONFIG_SOC_SERIES_IMXRT10XX) || defined(CONFIG_SOC_SERIES_IMXRT118X) KEEP(*(.boot_hdr.conf)) #endif -#if defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX) +#if defined(CONFIG_SOC_SERIES_IMXRT6XX) || defined(CONFIG_SOC_SERIES_IMXRT5XX) || defined(CONFIG_SOC_SERIES_IMXRT7XX) KEEP(*(.flash_conf)) #endif #if defined(CONFIG_SOC_SERIES_IMXRT118X) diff --git a/soc/nxp/imxrt/imxrt5xx/cm33/pinctrl_soc.h b/soc/nxp/imxrt/imxrt5xx/cm33/pinctrl_soc.h index 3389073bd09a60..c60d888b5b2fc2 100644 --- a/soc/nxp/imxrt/imxrt5xx/cm33/pinctrl_soc.h +++ b/soc/nxp/imxrt/imxrt5xx/cm33/pinctrl_soc.h @@ -1,5 +1,5 @@ /* - * Copyright 2022, NXP + * Copyright 2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,11 +31,6 @@ typedef uint32_t pinctrl_soc_pin_t; IOPCTL_PIO_IIENA(DT_PROP(node_id, nxp_invert)) | /* invert input */ \ IOPCTL_PIO_AMENA(DT_PROP(node_id, nxp_analog_mode))) /* analog multiplexor */ -/* MCUX RT parts only have one pin type */ -#define Z_PINCTRL_IOCON_D_PIN_MASK (0xFFF) -#define Z_PINCTRL_IOCON_A_PIN_MASK (0) -#define Z_PINCTRL_IOCON_I_PIN_MASK (0) - #define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \ DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_IOPCTL_PINCFG(group), diff --git a/soc/nxp/imxrt/imxrt6xx/pinctrl_soc.h b/soc/nxp/imxrt/imxrt6xx/pinctrl_soc.h index 445bd1a873b947..ba2a042de18cea 100644 --- a/soc/nxp/imxrt/imxrt6xx/pinctrl_soc.h +++ b/soc/nxp/imxrt/imxrt6xx/pinctrl_soc.h @@ -1,5 +1,5 @@ /* - * Copyright 2022, NXP + * Copyright 2022,2024 NXP * * SPDX-License-Identifier: Apache-2.0 */ @@ -31,11 +31,6 @@ typedef uint32_t pinctrl_soc_pin_t; IOPCTL_PIO_IIENA(DT_PROP(node_id, nxp_invert)) | /* invert input */ \ IOPCTL_PIO_AMENA(DT_PROP(node_id, nxp_analog_mode))) /* analog multiplexor */ -/* MCUX RT parts only have one pin type */ -#define Z_PINCTRL_IOCON_D_PIN_MASK (0xFFF) -#define Z_PINCTRL_IOCON_A_PIN_MASK (0) -#define Z_PINCTRL_IOCON_I_PIN_MASK (0) - #define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \ DT_PROP_BY_IDX(group, pin_prop, idx) | Z_PINCTRL_IOPCTL_PINCFG(group), diff --git a/soc/nxp/imxrt/imxrt7xx/CMakeLists.txt b/soc/nxp/imxrt/imxrt7xx/CMakeLists.txt new file mode 100644 index 00000000000000..6514fc58b31bec --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/CMakeLists.txt @@ -0,0 +1,9 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +if (CONFIG_SOC_MIMXRT798S_CM33_CPU0 OR CONFIG_SOC_MIMXRT798S_CM33_CPU1) + add_subdirectory(cm33) +endif() diff --git a/soc/nxp/imxrt/imxrt7xx/Kconfig b/soc/nxp/imxrt/imxrt7xx/Kconfig new file mode 100644 index 00000000000000..f416ab4beb2c2b --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/Kconfig @@ -0,0 +1,57 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_MIMXRT798S_CM33_CPU0 + select CPU_CORTEX_M33 + select CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select ARM + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_MCUX + select HAS_MCUX_SYSCON + select HAS_MCUX_CACHE + select HAS_GLIKEY + select SOC_RESET_HOOK + +config SOC_MIMXRT798S_CM33_CPU1 + select CPU_CORTEX_M33 + select CLOCK_CONTROL + select CPU_CORTEX_M_HAS_DWT + select ARM + select CPU_HAS_ARM_SAU + select CPU_HAS_ARM_MPU + select CPU_HAS_FPU + select ARMV8_M_DSP + select ARM_TRUSTZONE_M + select CPU_CORTEX_M_HAS_SYSTICK + select HAS_MCUX + select HAS_MCUX_SYSCON + select HAS_GLIKEY + select SOC_RESET_HOOK + +if SOC_SERIES_IMXRT7XX + +if NXP_IMXRT_BOOT_HEADER + +config IMAGE_VECTOR_TABLE_OFFSET + default 0x4000 + +endif # NXP_IMXRT_BOOT_HEADER + +config IMXRT7XX_CODE_CACHE + bool "Code cache" + default y if HAS_MCUX_CACHE + help + Enable code cache for XSPI region at boot. If this Kconfig is + cleared, the CACHE64 controller will be disabled during SOC init + +config MCUX_CORE_SUFFIX + default "_cm33_core0" if SOC_MIMXRT798S_CM33_CPU0 + default "_cm33_core1" if SOC_MIMXRT798S_CM33_CPU1 + +endif # SOC_SERIES_IMXRT7XX diff --git a/soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig b/soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig new file mode 100644 index 00000000000000..5d5466b182cd2d --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig @@ -0,0 +1,29 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +if SOC_MIMXRT798S_CM33_CPU0 + +config ROM_START_OFFSET + default 0x4000 if NXP_IMXRT_BOOT_HEADER + +config NUM_IRQS + default 158 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 237500000 if CORTEX_M_SYSTICK + +endif # SOC_MIMXRT798S_CM33_CPU0 + +if SOC_MIMXRT798S_CM33_CPU1 + +config NUM_IRQS + default 93 + +config SYS_CLOCK_HW_CYCLES_PER_SEC + default 100000000 if CORTEX_M_SYSTICK + +endif # SOC_MIMXRT798S_CM33_CPU1 + +config MFD + default y + depends on DT_HAS_NXP_LP_FLEXCOMM_ENABLED diff --git a/soc/nxp/imxrt/imxrt7xx/Kconfig.soc b/soc/nxp/imxrt/imxrt7xx/Kconfig.soc new file mode 100644 index 00000000000000..5e321bdc9bb26b --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/Kconfig.soc @@ -0,0 +1,50 @@ +# Copyright 2024 NXP +# SPDX-License-Identifier: Apache-2.0 + +config SOC_SERIES_IMXRT7XX + bool + select SOC_FAMILY_NXP_IMXRT + +config SOC_MIMXRT798S + bool + select SOC_SERIES_IMXRT7XX + +config SOC_MIMXRT798S_CM33_CPU0 + bool + select SOC_MIMXRT798S + +config SOC_MIMXRT798S_CM33_CPU1 + bool + select SOC_MIMXRT798S + +config SOC_SERIES + default "imxrt7xx" if SOC_SERIES_IMXRT7XX + +config SOC + default "mimxrt798s" if SOC_MIMXRT798S + +config SOC_PART_NUMBER_MIMXRT798SGAWAR + bool + +config SOC_PART_NUMBER_MIMXRT798SGFOA + bool + +config SOC_PART_NUMBER_MIMXRT758SGAWAR + bool + +config SOC_PART_NUMBER_MIMXRT758SGFOA + bool + +config SOC_PART_NUMBER_MIMXRT735SGAWAR + bool + +config SOC_PART_NUMBER_MIMXRT735SGFOA + bool + +config SOC_PART_NUMBER + default "MIMXRT798SGFOA" if SOC_PART_NUMBER_MIMXRT798SGFOA + default "MIMXRT798SGAWAR" if SOC_PART_NUMBER_MIMXRT798SGAWAR + default "MIMXRT758SGFOA" if SOC_PART_NUMBER_MIMXRT758SGFOA + default "MIMXRT758SGAWAR" if SOC_PART_NUMBER_MIMXRT758SGAWAR + default "MIMXRT735SGFOA" if SOC_PART_NUMBER_MIMXRT735SGFOA + default "MIMXRT735SGAWAR" if SOC_PART_NUMBER_MIMXRT735SGAWAR diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt b/soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt new file mode 100644 index 00000000000000..cd9319bffaaf4a --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/cm33/CMakeLists.txt @@ -0,0 +1,25 @@ +# +# Copyright 2024 NXP +# +# SPDX-License-Identifier: Apache-2.0 +# + +zephyr_compile_definitions_ifdef(CONFIG_NXP_LP_FLEXCOMM LPFLEXCOMM_INIT_NOT_USED_IN_DRIVER=1) + +zephyr_compile_definitions(FSL_SDK_DRIVER_QUICK_ACCESS_ENABLE) + +zephyr_include_directories(.) + +zephyr_sources(soc.c) + +if(CONFIG_FLASH_MCUX_XSPI_XIP) + zephyr_sources(flash_clock_setup.c) + zephyr_code_relocate(FILES flash_clock_setup.c LOCATION ${CONFIG_FLASH_MCUX_XSPI_XIP_MEM}_TEXT) +endif() + +zephyr_library_include_directories( + ${ZEPHYR_BASE}/kernel/include + ${ZEPHYR_BASE}/arch/${ARCH}/include + ) + +set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "") diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/flash_clock_setup.c b/soc/nxp/imxrt/imxrt7xx/cm33/flash_clock_setup.c new file mode 100644 index 00000000000000..9994fc3885f293 --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/cm33/flash_clock_setup.c @@ -0,0 +1,168 @@ +/* + * Copyright 2024 NXP + * SPDX-License-Identifier: Apache-2.0 + */ + +#include +#include + +#ifdef CONFIG_HAS_MCUX_CACHE +#include +#endif + +static void enable_xspi_cache(CACHE64_CTRL_Type *cache) +{ + /* First, invalidate the entire cache. */ + cache->CCR |= CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK | + CACHE64_CTRL_CCR_GO_MASK; + while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + cache->CCR &= ~(CACHE64_CTRL_CCR_INVW0_MASK | CACHE64_CTRL_CCR_INVW1_MASK); + /* Now enable the cache. */ + cache->CCR |= CACHE64_CTRL_CCR_ENCACHE_MASK; +} + +static void disable_xspi_cache(CACHE64_CTRL_Type *cache) +{ + cache->CCR |= CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK | + CACHE64_CTRL_CCR_GO_MASK; /* First, clean XSPI cache. */ + while ((cache->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0x00U) { + } + /* As a precaution clear the bits to avoid inadvertently re-running this command. */ + cache->CCR &= ~(CACHE64_CTRL_CCR_PUSHW0_MASK | CACHE64_CTRL_CCR_PUSHW1_MASK); + + /* Now disable XSPI cache. */ + cache->CCR &= ~CACHE64_CTRL_CCR_ENCACHE_MASK; +} + +static void flash_deinit(XSPI_Type *base, CACHE64_CTRL_Type *cache) +{ + if (base == XSPI0) { + /* Enable clock again. */ + CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_CLR_XSPI0_MASK; + } else if (base == XSPI1) { + /* Enable clock again. */ + CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_CLR_XSPI1_MASK; + } + + base->MCR &= ~XSPI_MCR_MDIS_MASK; + if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) != 0x00U) { + disable_xspi_cache(cache); + } + /* Wait until XSPI is not busy */ + while ((base->SR & XSPI_SR_BUSY_MASK) != 0U) { + } + /* Disable module. */ + base->MCR |= XSPI_MCR_MDIS_MASK; +} + +static void flash_init(XSPI_Type *base, CACHE64_CTRL_Type *cache) +{ + /* Enable XSPI module */ + base->MCR |= XSPI_MCR_MDIS_MASK; + + base->MCR |= XSPI_MCR_SWRSTSD_MASK | XSPI_MCR_SWRSTHD_MASK; + for (uint32_t i = 0; i < 6; i++) { + __NOP(); + } + base->MCR &= ~(XSPI_MCR_SWRSTSD_MASK | XSPI_MCR_SWRSTHD_MASK); + base->MCR |= XSPI_MCR_IPS_TG_RST_MASK | XSPI_MCR_MDIS_MASK; + base->MCR &= ~XSPI_MCR_ISD3FA_MASK; + base->MCR &= ~XSPI_MCR_MDIS_MASK; + base->MCR |= XSPI_MCR_MDIS_MASK; + base->MCR |= XSPI_MCR_ISD3FA_MASK; + base->MCR &= ~XSPI_MCR_MDIS_MASK; + + base->MCR |= XSPI_MCR_MDIS_MASK; + base->SMPR = (((base->SMPR) & (~XSPI_SMPR_DLLFSMPFA_MASK)) | + XSPI_SMPR_DLLFSMPFA(FSL_FEATURE_XSPI_DLL_REF_VALUE_DDR_DELAY_TAP_NUM)); + base->MCR &= ~XSPI_MCR_MDIS_MASK; + + base->DLLCR[0] &= + ~(XSPI_DLLCR_SLV_DLL_BYPASS_MASK | XSPI_DLLCR_DLL_CDL8_MASK | + XSPI_DLLCR_SLV_DLY_OFFSET_MASK | XSPI_DLLCR_SLV_FINE_OFFSET_MASK | + XSPI_DLLCR_DLLRES_MASK | XSPI_DLLCR_DLL_REFCNTR_MASK | XSPI_DLLCR_FREQEN_MASK); + base->DLLCR[0] &= + ~(XSPI_DLLCR_SLV_EN_MASK | XSPI_DLLCR_SLAVE_AUTO_UPDT_MASK | XSPI_DLLCR_DLLEN_MASK); + /* Enable subordinate as auto update mode. */ + base->DLLCR[0] |= XSPI_DLLCR_SLV_EN_MASK | XSPI_DLLCR_SLAVE_AUTO_UPDT_MASK; + /* program DLL to desired delay. */ + base->DLLCR[0] |= + XSPI_DLLCR_DLLRES(FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_X16_DISABLE_RES) | + XSPI_DLLCR_DLL_REFCNTR( + FSL_FEATURE_XSPI_DLL_REF_VALUE_AUTOUPDATE_X16_DISABLED_REF_COUNTER) | + XSPI_DLLCR_SLV_FINE_OFFSET(0) | XSPI_DLLCR_SLV_DLY_OFFSET(0) | + XSPI_DLLCR_FREQEN(1U); + /* Load above settings into delay chain. */ + base->DLLCR[0] |= XSPI_DLLCR_SLV_UPD_MASK; + base->DLLCR[0] |= XSPI_DLLCR_DLLEN_MASK; + base->DLLCR[0] &= ~XSPI_DLLCR_SLV_UPD_MASK; + + while ((base->DLLSR & XSPI_DLLSR_SLVA_LOCK_MASK) == 0UL) { + } + + if ((cache->CCR & CACHE64_CTRL_CCR_ENCACHE_MASK) == 0x00U) { + enable_xspi_cache(cache); + /* flush pipeline */ + __DSB(); + __ISB(); + } +} + +/* xspi_setup_clock run in RAM when XIP. */ +void xspi_setup_clock(XSPI_Type *base, uint32_t src, uint32_t divider) +{ + if (base == XSPI0) { + if ((CLKCTL0->XSPI0FCLKSEL != CLKCTL0_XSPI0FCLKSEL_SEL(src)) || + ((CLKCTL0->XSPI0FCLKDIV & CLKCTL0_XSPI0FCLKDIV_DIV_MASK) != (divider - 1))) { + /* Always deinit XSPI and init XSPI for the flash to make + * sure the flash works correctly after the XSPI root clock + * changed as the default XSPI configuration may does not + * work for the new root clock frequency. + */ + flash_deinit(base, CACHE64_CTRL0); + + /* Disable clock before changing clock source */ + CLKCTL0->PSCCTL1_CLR = CLKCTL0_PSCCTL1_CLR_XSPI0_MASK; + /* Update XSPI clock. */ + CLKCTL0->XSPI0FCLKSEL = + CLKCTL0_XSPI0FCLKSEL_SEL(src) | CLKCTL0_XSPI0FCLKSEL_SEL_EN_MASK; + CLKCTL0->XSPI0FCLKDIV = CLKCTL0_XSPI0FCLKDIV_DIV(divider - 1); + while ((CLKCTL0->XSPI0FCLKDIV) & CLKCTL0_XSPI0FCLKDIV_REQFLAG_MASK) { + } + /* Enable XSPI clock again */ + CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI0_MASK; + + flash_init(base, CACHE64_CTRL0); + } + } else if (base == XSPI1) { + if ((CLKCTL0->XSPI1FCLKSEL != CLKCTL0_XSPI1FCLKSEL_SEL(src)) || + ((CLKCTL0->XSPI1FCLKDIV & CLKCTL0_XSPI1FCLKDIV_DIV_MASK) != (divider - 1))) { + /* Always deinit XSPI and init XSPI for the flash to make sure the flash + * works correctly after the XSPI root clock changed as the default XSPI + * configuration may does not work for the new root clock frequency. + */ + flash_deinit(base, CACHE64_CTRL1); + + /* Disable clock before changing clock source */ + CLKCTL0->PSCCTL1_CLR = CLKCTL0_PSCCTL1_CLR_XSPI1_MASK; + /* Update XSPI clock. */ + CLKCTL0->XSPI1FCLKSEL = + CLKCTL0_XSPI1FCLKSEL_SEL(src) | CLKCTL0_XSPI1FCLKSEL_SEL_EN_MASK; + CLKCTL0->XSPI1FCLKDIV = CLKCTL0_XSPI1FCLKDIV_DIV(divider - 1); + while ((CLKCTL0->XSPI1FCLKDIV) & CLKCTL0_XSPI1FCLKDIV_REQFLAG_MASK) { + } + /* Enable XSPI clock again */ + CLKCTL0->PSCCTL1_SET = CLKCTL0_PSCCTL1_SET_XSPI1_MASK; + + flash_init(base, CACHE64_CTRL1); + } + } +} + +void xspi_clock_safe_config(void) +{ + xspi_setup_clock(XSPI0, 0U, 1U); + xspi_setup_clock(XSPI1, 0U, 1U); +} diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/pinctrl_soc.h b/soc/nxp/imxrt/imxrt7xx/cm33/pinctrl_soc.h new file mode 100644 index 00000000000000..4627eaf0edb353 --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/cm33/pinctrl_soc.h @@ -0,0 +1,82 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +#ifndef ZEPHYR_SOC_ARM_NXP_IMX_RT7XX_PINCTRL_SOC_H_ +#define ZEPHYR_SOC_ARM_NXP_IMX_RT7XX_PINCTRL_SOC_H_ + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** @cond INTERNAL_HIDDEN */ + +typedef uint32_t pinctrl_soc_pin_t; + +#define IOPCTL_PIO_PUPDENA_MASK (0x10U) +#define IOPCTL_PIO_PUPDSEL_MASK (0x20U) + +#define IOPCTL_PIO_ODENA_MASK (0x400U) +#define IOPCTL_PIO_ODENA_SHIFT (10U) +#define IOPCTL_PIO_ODENA(x) \ + (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_ODENA_SHIFT)) & IOPCTL_PIO_ODENA_MASK) + +#define IOPCTL_PIO_IBENA_MASK (0x40U) +#define IOPCTL_PIO_IBENA_SHIFT (6U) +#define IOPCTL_PIO_IBENA(x) \ + (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_IBENA_SHIFT)) & IOPCTL_PIO_IBENA_MASK) + +/* Please note there is no SLEWRATE attribution on IOPCTL2 */ +#define IOPCTL_PIO_SLEWRATE_MASK (0x80U) +#define IOPCTL_PIO_SLEWRATE_SHIFT (7U) +#define IOPCTL_PIO_SLEWRATE(x) \ + (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_SLEWRATE_SHIFT)) & IOPCTL_PIO_SLEWRATE_MASK) + +/* Please note there is no FULLDRIVE attribution on IOPCTL2 */ +#define IOPCTL_PIO_FULLDRIVE_MASK (0x100U) +#define IOPCTL_PIO_FULLDRIVE_SHIFT (8U) +#define IOPCTL_PIO_FULLDRIVE(x) \ + (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_FULLDRIVE_SHIFT)) & IOPCTL_PIO_FULLDRIVE_MASK) + +#define IOPCTL_PIO_IIENA_MASK (0x800U) +#define IOPCTL_PIO_IIENA_SHIFT (11U) +#define IOPCTL_PIO_IIENA(x) \ + (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_IIENA_SHIFT)) & IOPCTL1_PIO_IIENA_MASK) + +/* Please note there is no AMENA attribution on IOPCTL2 */ +#define IOPCTL_PIO_AMENA_MASK (0x200U) +#define IOPCTL_PIO_AMENA_SHIFT (9U) +#define IOPCTL_PIO_AMENA(x) \ + (((uint32_t)(((uint32_t)(x)) << IOPCTL_PIO_AMENA_SHIFT)) & IOPCTL_PIO_AMENA_MASK) + +#define Z_PINCTRL_IOPCTL_PINCFG(node_id) \ + (IF_ENABLED(DT_PROP(node_id, bias_pull_down), \ + (IOPCTL_PIO_PUPDENA_MASK |)) /* pull down */ \ + IF_ENABLED(DT_PROP(node_id, bias_pull_up), \ + (IOPCTL_PIO_PUPDENA_MASK | IOPCTL_PIO_PUPDSEL_MASK |)) /* pull up */ \ + IOPCTL_PIO_ODENA(DT_PROP(node_id, drive_open_drain)) | /* open drain */ \ + IOPCTL_PIO_IBENA(DT_PROP(node_id, input_enable)) | /* input buffer */ \ + IOPCTL_PIO_SLEWRATE(DT_ENUM_IDX(node_id, slew_rate)) | /* slew rate */ \ + IOPCTL_PIO_FULLDRIVE( \ + DT_ENUM_IDX(node_id, drive_strength)) | /* drive strength */ \ + IOPCTL_PIO_IIENA(DT_PROP(node_id, nxp_invert)) | /* invert input */ \ + IOPCTL_PIO_AMENA( \ + DT_PROP(node_id, nxp_analog_mode))) /* analog multiplexor */ + +#define Z_PINCTRL_STATE_PIN_INIT(group, pin_prop, idx) \ + DT_PROP_BY_IDX(group, pin_prop, idx), + +#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \ + {DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \ + Z_PINCTRL_STATE_PIN_INIT)} + +#ifdef __cplusplus +} +#endif + +#endif /* ZEPHYR_SOC_ARM_NXP_IMX_RT7XX_PINCTRL_SOC_H_ */ diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/soc.c b/soc/nxp/imxrt/imxrt7xx/cm33/soc.c new file mode 100644 index 00000000000000..d8675dd02db56d --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/cm33/soc.c @@ -0,0 +1,27 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief System/hardware module for NXP RT7XX platform + * + * This module provides routines to initialize and support board-level + * hardware for the RT7XX platforms. + */ + +#include +#include +#include +#include + +#ifdef CONFIG_SOC_RESET_HOOK + +void soc_reset_hook(void) +{ + SystemInit(); +} + +#endif /* CONFIG_SOC_RESET_HOOK */ diff --git a/soc/nxp/imxrt/imxrt7xx/cm33/soc.h b/soc/nxp/imxrt/imxrt7xx/cm33/soc.h new file mode 100644 index 00000000000000..777c19f435cff1 --- /dev/null +++ b/soc/nxp/imxrt/imxrt7xx/cm33/soc.h @@ -0,0 +1,36 @@ +/* + * Copyright 2024 NXP + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Board configuration macros for the MIMXRT7XX platform + * + * This header file is used to specify and describe board-level aspects for the + * 'MIMXRT7XX' platform. + */ + +#ifndef _SOC__H_ +#define _SOC__H_ + +#ifndef _ASMLANGUAGE + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +void xspi_clock_safe_config(void); +void xspi_setup_clock(XSPI_Type *base, uint32_t src, uint32_t divider); + +#ifdef __cplusplus +} +#endif + +#endif /* !_ASMLANGUAGE */ + +#endif /* _SOC__H_ */ diff --git a/soc/nxp/imxrt/soc.yml b/soc/nxp/imxrt/soc.yml index 2fd2a0df226d35..98a9a9c82dff02 100644 --- a/soc/nxp/imxrt/soc.yml +++ b/soc/nxp/imxrt/soc.yml @@ -38,6 +38,14 @@ family: - name: mimxrt685s cpuclusters: - name: cm33 + - name: imxrt7xx + socs: + - name: mimxrt798s + cpuclusters: + - name: cm33_cpu0 + - name: cm33_cpu1 + - name: hifi1 + - name: hifi4 runners: run_once: '--erase': diff --git a/soc/sensry/ganymed/sy1xx/common/linker.ld b/soc/sensry/ganymed/sy1xx/common/linker.ld index 49b38680a41603..c9a08957c81018 100644 --- a/soc/sensry/ganymed/sy1xx/common/linker.ld +++ b/soc/sensry/ganymed/sy1xx/common/linker.ld @@ -78,6 +78,9 @@ SECTIONS #include + #ifdef CONFIG_LLEXT + #include + #endif SECTION_PROLOGUE(.plt,,) { diff --git a/west.yml b/west.yml index 87657ebf6df364..8b70f2404ee9be 100644 --- a/west.yml +++ b/west.yml @@ -198,7 +198,7 @@ manifest: groups: - hal - name: hal_nxp - revision: 3c64cd63125c86870802a561ce79dc33697b005c + revision: pull/444/head path: modules/hal/nxp groups: - hal