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Bug: Issue with PUTSP and HALT trap subroutines #13

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Bartor495 opened this issue Nov 18, 2021 · 0 comments
Open

Bug: Issue with PUTSP and HALT trap subroutines #13

Bartor495 opened this issue Nov 18, 2021 · 0 comments

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@Bartor495
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Under the current implementation, PUTSP only outputs ASCII values for bits 7-0 until bits 15-8 or the following memory location bits 7-0 are null. Additionally, HALT does not save the previous values of R0 and R1 at the time the processor halts.

The modified lc3_os.js file below should provide the needed fixes.

In this file PUTSP will perform bitwise AND on bits 15-8 with bit shifting and branches for sorting, and implement bitwise ADD with bit shifting on bits 7-0. Once the bitwise AND register becomes zero due to overflow, it will branch to checking monitor status and writing the character to the monitor before moving on to the next memory location.

HALT will change the register for storing the instruction to halt the processor from R0 to R7, and relocate loading R0 and R1 with the stored values to before the processor halt STI. This will allow R0 and R1 to keep their previous values so the operator does not have to place a breakpoint on the halt function to read these values.

lc3_os.zip

@Bartor495 Bartor495 changed the title Issue with PUTSP and HALT trap subroutines Bug: Issue with PUTSP and HALT trap subroutines Nov 18, 2021
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