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spc700.c
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spc700.c
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/****************************************************
*Part of SPC2IT, read readme.md for more information*
****************************************************/
/*
SNEeSe, an Open Source Super NES emulator.
Copyright (c) 1998-2006, Charles Bilyue'.
Portions copyright (c) 1998-2003, Brad Martin.
Portions copyright (c) 2003-2004, Daniel Horchner.
Portions copyright (c) 2004-2005, Nach. ( http://nsrt.edgeemu.com/ )
Unzip Technology, copyright (c) 1998 Gilles Vollant.
zlib Technology ( www.gzip.org/zlib/ ), Copyright (c) 1995-2003,
Jean-loup Gailly ( jloup* *at* *gzip.org ) and Mark Adler
( madler* *at* *alumni.caltech.edu ).
JMA Technology, copyright (c) 2004-2005 NSRT Team. ( http://nsrt.edgeemu.com/ )
LZMA Technology, copyright (c) 2001-4 Igor Pavlov. ( http://www.7-zip.org )
Portions copyright (c) 2002 Andrea Mazzoleni. ( http://advancemame.sf.net )
This is free software. See './doc/LICENSE_SNEESE' for details.
You must read and accept the license prior to use.
*/
#define SNEeSe_apu_spc700_c
#include "sneese_spc.h"
SPC700_CONTEXT primary_context;
SPC700_CONTEXT *active_context = &primary_context;
/*
SNEeSe SPC700 CPU emulation core
Originally written by Lee Hammerton in AT&T assembly
Maintained/rewritten/ported to NASM by Charles Bilyue'
Maintained/ported to C by Charles Bilyue'
This file contains:
CPU core info
Reset
Execution Loop
Invalid Opcode Handler or Dispatcher
Variable definitions (registers, cycle counters, etc.)
CPU opcode emulation handlers
CPU opcode handler table
CPU opcode timing table
CPU core info:
A register - active_context->YA.b.A
Y register - active_context->YA.b.Y
YA register pair - active_context->YA.w
X register - active_context->X
Stack pointer - active_context->SP
Program Counter - active_context->PC
Processor status word - active_context->PSW
Individual flags - N_flag, V_flag, P_flag, B_flag,
H_flag, I_flag, Z_flag, C_flag
SPC timers
SPC700 timing is not directly related to 65c816 timing, but for
simplicity in emulation we act as if it is. SPC700 gets 5632
cycles for every 118125 (21.47727..MHz) 5A22 cycles. Since the
timers run at ~8KHz and ~64KHz and the CPU core runs at
1.024Mhz, the timers are clocked as follows:
1.024MHz / 8KHz = 128 cycles (Timers 0 and 1)
1.024MHz / 64KHz = 16 cycles (Timer 2)
*/
/* lots of #define's! */
/* These are the bits for flag set/clr operations */
#define SPC_FLAG_C 1 /* Carry */
#define SPC_FLAG_Z 2 /* Zero result */
#define SPC_FLAG_I 4 /* Interrupt Disable */
#define SPC_FLAG_H 8 /* Half-carry */
#define SPC_FLAG_B 0x10 /* Break */
#define SPC_FLAG_P 0x20 /* Page (direct page) */
#define SPC_FLAG_V 0x40 /* Overflow */
#define SPC_FLAG_N 0x80 /* Negative result */
#define SPC_FLAG_NZ (SPC_FLAG_N | SPC_FLAG_Z)
#define SPC_FLAG_NZC (SPC_FLAG_NZ | SPC_FLAG_C)
#define SPC_FLAG_NHZC (SPC_FLAG_NZC | SPC_FLAG_H)
#define _Cycles (active_context->Cycles)
#define _last_cycles (active_context->last_cycles)
#define _TotalCycles (active_context->TotalCycles)
#define _WorkCycles (active_context->WorkCycles)
#define _PORT_R (active_context->PORT_R)
#define _PORT0R (_PORT_R[0])
#define _PORT1R (_PORT_R[1])
#define _PORT2R (_PORT_R[2])
#define _PORT3R (_PORT_R[3])
#define _PORT_W (active_context->PORT_W)
#define _PORT0W (_PORT_W[0])
#define _PORT1W (_PORT_W[1])
#define _PORT2W (_PORT_W[2])
#define _PORT3W (_PORT_W[3])
#define _FFC0_Address (active_context->FFC0_Address)
#define _PC (active_context->PC.w)
#define _PCL (active_context->PC.b.l)
#define _PCH (active_context->PC.b.h)
#define _YA (active_context->YA.w)
#define _A (active_context->YA.b.l)
#define _Y (active_context->YA.b.h)
#define _dp (active_context->direct_page.w)
#define _direct_page (active_context->direct_page.b.h)
#define _SP (active_context->SP)
#define _X (active_context->X)
#define _PSW (active_context->PSW)
#define _cycle (active_context->cycle)
#define _opcode (active_context->opcode)
#define _data (active_context->data)
#define _data2 (active_context->data2)
#define _data16 (active_context->data16.w)
#define _offset (active_context->offset)
#define _address (active_context->address.w)
#define _address_l (active_context->address.b.l)
#define _address_h (active_context->address.b.h)
#define _address2 (active_context->address2.w)
#define _address2_l (active_context->address2.b.l)
#define _address2_h (active_context->address2.b.h)
#define _N_flag (active_context->N_flag)
#define _V_flag (active_context->V_flag)
#define _P_flag (active_context->P_flag)
#define _B_flag (active_context->B_flag)
#define _H_flag (active_context->H_flag)
#define _I_flag (active_context->I_flag)
#define _Z_flag (active_context->Z_flag)
#define _C_flag (active_context->C_flag)
#define _timers (active_context->timers)
/* bits used all over the core */
void set_flag_spc(u8 flag)
{
if (flag & SPC_FLAG_N)
{
_N_flag = 0x80;
}
if (flag & SPC_FLAG_V)
{
_V_flag = 1;
}
if (flag & SPC_FLAG_P)
{
_P_flag = 1;
_direct_page = 0x01;
}
if (flag & SPC_FLAG_B)
{
_B_flag = 1;
}
if (flag & SPC_FLAG_H)
{
_H_flag = 1;
}
if (flag & SPC_FLAG_I)
{
_I_flag = 1;
}
if (flag & SPC_FLAG_Z)
{
_Z_flag = 0;
}
if (flag & SPC_FLAG_C)
{
_C_flag = 1;
}
}
void clr_flag_spc(u8 flag)
{
if (flag & SPC_FLAG_N)
{
_N_flag = 0;
}
if (flag & SPC_FLAG_V)
{
_V_flag = 0;
}
if (flag & SPC_FLAG_P)
{
_P_flag = 0;
_direct_page = 0x00;
}
if (flag & SPC_FLAG_B)
{
_B_flag = 0;
}
if (flag & SPC_FLAG_H)
{
_H_flag = 0;
}
if (flag & SPC_FLAG_I)
{
_I_flag = 0;
}
if (flag & SPC_FLAG_Z)
{
_Z_flag = 1;
}
if (flag & SPC_FLAG_C)
{
_C_flag = 0;
}
}
void complement_carry_spc(void)
{
_C_flag = !_C_flag;
}
u8 flag_state_spc(u8 flag)
{
if (flag == SPC_FLAG_N)
{
return _N_flag & 0x80;
}
else if (flag == SPC_FLAG_V)
{
return _V_flag;
}
else if (flag == SPC_FLAG_P)
{
return _P_flag;
}
else if (flag == SPC_FLAG_B)
{
return _B_flag;
}
else if (flag == SPC_FLAG_H)
{
return _H_flag;
}
else if (flag == SPC_FLAG_I)
{
return _I_flag;
}
else if (flag == SPC_FLAG_Z)
{
return !_Z_flag;
}
else if (flag == SPC_FLAG_C)
{
return _C_flag;
}
return 0;
}
void load_cycles_spc(void)
{
_WorkCycles = _TotalCycles - _Cycles;
}
u32 get_cycles_spc(void)
{
return _WorkCycles + _Cycles;
}
void save_cycles_spc(void)
{
_TotalCycles = _WorkCycles + _Cycles;
}
/* Set up the flags from our flag format to SPC flag format */
void spc_setup_flags(s32 B_flag)
{
u8 PSW = 0;
PSW += _N_flag & 0x80;
PSW += _V_flag ? 0x40 : 0;
PSW += _P_flag ? 0x20 : 0;
PSW += B_flag ? 0x10 : 0;
PSW += _H_flag ? 0x08 : 0;
PSW += _I_flag ? 0x04 : 0;
PSW += !_Z_flag ? 0x02 : 0;
PSW += _C_flag ? 0x01 : 0;
_PSW = PSW;
}
/* Restore the flags from SPC flag format to our flag format */
void spc_restore_flags(void)
{
u8 PSW = _PSW;
_N_flag = PSW;
_V_flag = PSW & SPC_FLAG_V;
if (PSW & SPC_FLAG_P)
set_flag_spc(SPC_FLAG_P);
else
clr_flag_spc(SPC_FLAG_P);
_B_flag = PSW & SPC_FLAG_B;
_H_flag = PSW & SPC_FLAG_H;
_I_flag = PSW & SPC_FLAG_I;
_Z_flag = ~PSW & SPC_FLAG_Z;
_C_flag = PSW & SPC_FLAG_C;
}
void store_flag_n(u8 value)
{
_N_flag = value;
}
void store_flag_v(u8 value)
{
_V_flag = value;
}
void store_flag_p(u8 value)
{
_P_flag = value;
_direct_page = value ? 0x01 : 0x00;
}
void store_flag_h(u8 value)
{
_H_flag = value;
}
void store_flag_i(u8 value)
{
_I_flag = value;
}
void store_flag_z(u8 value)
{
_Z_flag = value;
}
void store_flag_c(u8 value)
{
_C_flag = value;
}
void store_flags_nz(u8 value)
{
store_flag_n(value);
store_flag_z(value);
}
void store_flags_nzc(u8 nz, u8 c)
{
store_flag_n(nz);
store_flag_z(nz);
store_flag_c(c);
}
/* bits for external access by the 5A22 core */
u8 SPC_READ_PORT_W(u16 address)
{
return _PORT_W[address & 3];
}
void SPC_WRITE_PORT_R(u16 address, u8 data)
{
_PORT_R[address & 3] = data;
}
/* bits for handling cycle counter overflows */
void Wrap_SPC_Cyclecounter()
{
_TotalCycles -= 0xF0000000;
_Cycles -= 0xF0000000;
_timers[0].cycle_latch -= 0xF0000000;
_timers[1].cycle_latch -= 0xF0000000;
_timers[2].cycle_latch -= 0xF0000000;
Wrap_SDSP_Cyclecounter();
}
/* This code should be mapped into the top of the address space */
static u8 SPC_ROM_CODE[64] = {0xCD, 0xEF, 0xBD, 0xE8, 0x00, 0xC6, 0x1D, 0xD0, 0xFC, 0x8F, 0xAA, 0xF4, 0x8F,
0xBB, 0xF5, 0x78, 0xCC, 0xF4, 0xD0, 0xFB, 0x2F, 0x19, 0xEB, 0xF4, 0xD0, 0xFC,
0x7E, 0xF4, 0xD0, 0x0B, 0xE4, 0xF5, 0xCB, 0xF4, 0xD7, 0x00, 0xFC, 0xD0, 0xF3,
0xAB, 0x01, 0x10, 0xEF, 0x7E, 0xF4, 0x10, 0xEB, 0xBA, 0xF6, 0xDA, 0x00, 0xBA,
0xF4, 0xC4, 0xF4, 0xDD, 0x5D, 0xD0, 0xDB, 0x1F, 0x00, 0x00, 0xC0, 0xFF};
static u8 SPC_READ_INVALID(u16 address)
{
#ifdef TRAP_INVALID_READ
#ifdef DEBUG
/* Set up address so message works */
Map_Address = address;
Map_Byte = 0;
InvalidSPCHWRead(); /* Display read from invalid HW warning */
#endif
#endif
return 0;
}
static u8 SPC_READ_RAM(u16 address)
{
return SPCRAM[address];
}
static u8 SPC_READ_DSP_DATA(u16 address)
{
SPC_READ_DSP();
/* read from DSP register */
/* DSP address bit 7 ignored during reads only! */
return SPC_DSP[SPC_DSP_ADDR & 0x7F];
}
u8 SPC_READ_PORT_R(u16 address)
{
return _PORT_R[address & 3];
}
/* timer registers are write-only, actual timer clock is internal and */
/* not accessible! */
/* counters are 4-bit, upon read/write they reset to 0 */
void Update_SPC_Timer(s32 timer)
{
u32 shift, mask, cycles, position;
if (timer != 2)
{
shift = 7;
}
else
{
shift = 4;
}
mask = -BIT(shift);
cycles = _TotalCycles - _timers[timer].cycle_latch;
_timers[timer].cycle_latch += cycles & mask;
/* nothing to do if timer turned off */
if (!(SPC_CTRL & BIT(timer)))
return;
position = _timers[timer].position + (cycles >> shift);
_timers[timer].position = position;
if (position < _timers[timer].target)
{
return;
}
_timers[timer].counter += position / _timers[timer].target;
/* 4-bit counter without saturation */
_timers[timer].counter &= 0x0F;
_timers[timer].position = position % _timers[timer].target;
}
static u8 SPC_READ_COUNTER(u16 address)
{
/* 0xFD = read address for first timer's counter */
s32 timer = address - 0xFD;
u8 counter;
Update_SPC_Timer(timer);
counter = _timers[timer].counter;
_timers[timer].counter = 0;
return counter;
}
/*
| ROMEN | ----- | PC32 | PC10 | ----- | ST2 | ST1 | ST0 |
ROMEN - enable mask ROM in top 64-bytes of address space for CPU read
PC32 - clear SPC read ports 2 & 3
PC10 - clear SPC read ports 0 & 1
ST2 - start timer 2 (64kHz)
ST1 - start timer 1 (8kHz)
ST0 - start timer 0 (8kHz)
*/
void spc_start_timer(s32 timer)
{
u32 shift, mask;
if (timer != 2)
{
shift = 7;
}
else
{
shift = 4;
}
mask = -BIT(shift);
_timers[timer].cycle_latch = _TotalCycles & mask;
_timers[timer].position = 0;
_timers[timer].counter = 0;
}
static void SPC_WRITE_INVALID(u16 address, u8 data)
{
#ifdef TRAP_INVALID_WRITE
#ifdef DEBUG
/* Set up address so message works */
Map_Address = address;
Map_Byte = data;
InvalidSPCHWWrite(); /* Display write to invalid HW warning */
#endif
#endif
}
static void SPC_WRITE_CTRL(u16 address, u8 data)
{
/* IPL ROM enable */
_FFC0_Address = data & 0x80 ? SPC_ROM_CODE - 0xFFC0 : SPCRAM;
/* read ports 0/1 reset */
if (data & 0x10)
{
_PORT_R[0] = 0;
_PORT_R[1] = 0;
}
/* read ports 2/3 reset */
if (data & 0x20)
{
_PORT_R[2] = 0;
_PORT_R[3] = 0;
}
/* timer 0 control */
if (!(SPCRAM[address] & 1) && (data & 1))
{
spc_start_timer(0);
}
/* timer 0 control */
if (!(SPCRAM[address] & 2) && (data & 2))
{
spc_start_timer(1);
}
/* timer 2 control */
if (!(SPCRAM[address] & 4) && (data & 4))
{
spc_start_timer(2);
}
SPC_CTRL = data;
}
static void SPC_WRITE_RAM(u16 address, u8 data)
{
SPCRAM[address] = data;
}
static void SPC_WRITE_DSP_DATA(u16 address, u8 data)
{
SPC_DSP_DATA = data;
/* write to DSP register */
SPC_WRITE_DSP();
}
void SPC_WRITE_PORT_W(u16 address, u8 data)
{
_PORT_W[address & 3] = data;
}
static void SPC_WRITE_TIMER(u16 address, u8 data)
{
/* 0xFA = write address for first timer's target */
s32 timer = address - 0xFA;
s32 target;
if ((_timers[timer].target & 0xFF) == data)
{
return;
}
target = data ? data : 256;
/* Timer must catch up before changing target */
Update_SPC_Timer(timer);
_timers[timer].target = target;
/* does setting target for current position raise counter? assuming not */
if (target <= _timers[timer].position)
/* handle 'delay' where new target is set below position */
{
_timers[timer].position -= 256;
}
}
/* Mappings for SPC Registers */
static u8 (*Read_Func_Map[16])(u16 address) = {SPC_READ_INVALID, SPC_READ_INVALID, SPC_READ_RAM, SPC_READ_DSP_DATA,
SPC_READ_PORT_R, SPC_READ_PORT_R, SPC_READ_PORT_R, SPC_READ_PORT_R,
SPC_READ_RAM, SPC_READ_RAM, SPC_READ_INVALID, SPC_READ_INVALID,
SPC_READ_INVALID, SPC_READ_COUNTER, SPC_READ_COUNTER, SPC_READ_COUNTER};
static void (*Write_Func_Map[16])(u16 address, u8 data) = {
SPC_WRITE_INVALID, SPC_WRITE_CTRL, SPC_WRITE_RAM, SPC_WRITE_DSP_DATA, SPC_WRITE_PORT_W, SPC_WRITE_PORT_W,
SPC_WRITE_PORT_W, SPC_WRITE_PORT_W, SPC_WRITE_RAM, SPC_WRITE_RAM, SPC_WRITE_TIMER, SPC_WRITE_TIMER,
SPC_WRITE_TIMER, SPC_WRITE_RAM, SPC_WRITE_RAM, SPC_WRITE_RAM};
static u8 offset_to_bit[8] = {0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80};
static u8 offset_to_not[8] = {0xFE, 0xFD, 0xFB, 0xF7, 0xEF, 0xDF, 0xBF, 0x7F};
u8 get_byte_spc(u16 address)
{
/* Note: need to update sound if echo write enabled and accessing echo */
/* region */
if (address >= 0x0100)
/* not zero page */
{
if (address >= 0xFFC0)
/* return ROM if it's mapped in, else RAM */
{
return ((u8 *)_FFC0_Address)[address];
}
/* return RAM */
return SPCRAM[address];
}
/* zero page */
if (address < 0xF0)
/* RAM */
{
return SPCRAM[address];
}
save_cycles_spc(); /* Set cycle counter */
return Read_Func_Map[address - 0xF0](address);
}
/* -------- */
void set_byte_spc(u16 address, u8 data)
{
/* Note: need to update sound always, since all (?) writes affect RAM */
if (address >= 0x0100 || address < 0xF0)
/* write to RAM */
{
save_cycles_spc(); /* Set cycle counter */
update_sound();
SPCRAM[address] = data;
}
else
{
save_cycles_spc(); /* Set cycle counter */
Write_Func_Map[address - 0xF0](address, data);
}
}
void Reset_SPC(void)
{
s32 i;
/* Get ROM reset vector and setup Program Counter */
_PC = SPC_ROM_CODE[0xFFFE - 0xFFC0] + (SPC_ROM_CODE[0xFFFF - 0xFFC0] << 8);
/* Reset cycle counts */
_TotalCycles = 6; /* 5-7 cycles before execution begins */
_Cycles = 0;
_last_cycles = 0;
_cycle = 0;
/* Reset SSMP registers */
_dp = 0; /* Used to save P flag check for dp addressing */
_SP = 0xEF;
_YA = 0;
_X = 0;
/* Clear flags register */
_PSW = 0;
clr_flag_spc(SPC_FLAG_N);
clr_flag_spc(SPC_FLAG_V);
clr_flag_spc(SPC_FLAG_P);
clr_flag_spc(SPC_FLAG_B);
clr_flag_spc(SPC_FLAG_H);
clr_flag_spc(SPC_FLAG_I);
clr_flag_spc(SPC_FLAG_Z);
clr_flag_spc(SPC_FLAG_C);
SPC_CTRL = 0x80;
_FFC0_Address = SPC_ROM_CODE - 0xFFC0;
/* Reset timers */
for (i = 0; i < 3; i++)
{
_timers[i].cycle_latch = 0;
_timers[i].position = 0;
_timers[i].target = 256;
_timers[i].counter = 0;
}
sound_cycle_latch = 0;
/* Reset SPC700 input ports */
_PORT_R[0] = 0;
_PORT_R[1] = 0;
_PORT_R[2] = 0;
_PORT_R[3] = 0;
/* Reset SPC700 output ports */
_PORT_W[0] = 0;
_PORT_W[1] = 0;
_PORT_W[2] = 0;
_PORT_W[3] = 0;
/* Reset sound DSP port address */
SPC_DSP_ADDR = 0;
SPC_DSP_DATA = 0;
}
void SPC_SHOW_REGISTERS(void)
{
DisplaySPC();
}
u8 get_SPC_PSW(void)
{
spc_setup_flags(_B_flag);
return _PSW;
}
#ifdef OPCODE_TRACE_LOG
#define SS_WAIT_FOR_KEY /*if ((readkey() & 0xFF) == 'g') { s32 i = 0; while (i++ < 49) simulate_keypress(' ' + \
(KEY_SPACE << 8)); }*/
#else
#define SS_WAIT_FOR_KEY
void dummy_fprintf()
{
}
#define fprintf dummy_fprintf
#endif
#ifdef OPCODE_TRACE_LOG
/* cycle #, PC, TotalCycles */
#define SINGLE_STEP_START(c) \
if (dump_flag && debug_log_file) \
{ \
fprintf(debug_log_file, "START_CYCLE(%u) PC:%04X %u\n", c, _PC & 0xFFFF, get_cycles_spc()); \
if ((c == 1) && (_PC == 0x02C4)) \
exit(0); \
}
void single_step_end(void)
{
if (!dump_flag || !debug_log_file)
return;
fprintf(debug_log_file, "NVPBHIZC R:%02X %02X %02X %02X X:%02X Y:%02X A:%02X SP:%02X dp:%02X Op:%02X\n",
_PORT0R & 0xFF, _PORT1R & 0xFF, _PORT2R & 0xFF, _PORT3R & 0xFF, _X & 0xFF, _Y & 0xFF, _A & 0xFF, _SP & 0xFF,
_direct_page & 0xFF, _opcode & 0xFF);
fprintf(debug_log_file, "%c%c%c%c%c%c%c%c W:%02X %02X %02X %02X Ad%04X %04X Off%02X D%02X %02X D16 %04X",
flag_state_spc(SPC_FLAG_N) ? '1' : '0', flag_state_spc(SPC_FLAG_V) ? '1' : '0',
flag_state_spc(SPC_FLAG_P) ? '1' : '0', flag_state_spc(SPC_FLAG_B) ? '1' : '0',
flag_state_spc(SPC_FLAG_H) ? '1' : '0', flag_state_spc(SPC_FLAG_I) ? '1' : '0',
flag_state_spc(SPC_FLAG_Z) ? '1' : '0', flag_state_spc(SPC_FLAG_C) ? '1' : '0', _PORT0W & 0xFF,
_PORT1W & 0xFF, _PORT2W & 0xFF, _PORT3W & 0xFF, _address & 0xFFFF, _address2 & 0xFFFF, _offset & 0xFF,
_data & 0xFF, _data2 & 0xFF, _data16 & 0xFFFF);
if (_cycle == 0)
fprintf(debug_log_file, " %s\n", SPC_OpID[_opcode]);
else
fprintf(debug_log_file, "\n");
}
/* op, R ports, W ports, X Y A */
/* address1 address2 offset data1 data2 data16 */
#define SINGLE_STEP_END single_step_end();
#else
#define SINGLE_STEP_START(c)
#define SINGLE_STEP_END
#endif
#define START_CYCLE(c) \
if (_cycle <= ((c)-1)) \
{ \
SINGLE_STEP_START(c)
#define END_FETCH_CYCLE() \
_WorkCycles++; \
SINGLE_STEP_END if (_WorkCycles >= 0) \
{ \
_cycle = 1; \
opcode_done = 0; \
break; \
} \
}
#define END_CYCLE(c, n) \
_WorkCycles += n; \
SINGLE_STEP_END if (_WorkCycles >= 0) \
{ \
_cycle = c; \
opcode_done = 0; \
break; \
} \
}
#define EXIT_OPCODE(n) \
{ \
_WorkCycles += n; \
SINGLE_STEP_END break; \
}
#define END_OPCODE(n) \
EXIT_OPCODE(n) \
}
#define END_BRANCH_OPCODE(cycle, TEST) \
TEST END_CYCLE((cycle), 1) \
\
/* sign extend offset and add to PC */ \
START_CYCLE((cycle)+1) _address = _PC + (((s32)_offset ^ 0x80) - 0x80); \
END_CYCLE((cycle)+1, 1) \
\
START_CYCLE((cycle)+2) \
_PC = _address; \
END_OPCODE(1)
#define REL_TEST_BRA ;
#define REL_TEST_BPL \
if (flag_state_spc(SPC_FLAG_N)) \
EXIT_OPCODE(1)
#define REL_TEST_BMI \
if (!flag_state_spc(SPC_FLAG_N)) \
EXIT_OPCODE(1)
#define REL_TEST_BVC \
if (flag_state_spc(SPC_FLAG_V)) \
EXIT_OPCODE(1)
#define REL_TEST_BVS \
if (!flag_state_spc(SPC_FLAG_V)) \
EXIT_OPCODE(1)
#define REL_TEST_BCC \
if (flag_state_spc(SPC_FLAG_C)) \
EXIT_OPCODE(1)
#define REL_TEST_BCS \
if (!flag_state_spc(SPC_FLAG_C)) \
EXIT_OPCODE(1)
#define REL_TEST_BNE \
if (flag_state_spc(SPC_FLAG_Z)) \
EXIT_OPCODE(1)
#define REL_TEST_BEQ \
if (!flag_state_spc(SPC_FLAG_Z)) \
EXIT_OPCODE(1)
#define OP_TCALL(vector) \
/* 8 cycles - opcode, new PCL, new PCH, stack address load, PCH */ \
/* write, PCL write, dummy cycle (PSW write in BRK?) */ \
/* SP decrement */ \
/* fetch address for PC */ \
START_CYCLE(2) \
_address = 0xFFC0 + ((15 - (vector)) * 2); \
_address2 = get_byte_spc(_address); \
END_CYCLE(2, 1) \
\
START_CYCLE(3) \
_address2 += (get_byte_spc(_address + 1) << 8); \
END_CYCLE(3, 1) \
\
START_CYCLE(4) \
_address = 0x0100 + _SP; \
END_CYCLE(4, 1) \
\
START_CYCLE(5) \
set_byte_spc(_address, _PC >> 8); \
_SP--; \
_address = 0x0100 + _SP; \
END_CYCLE(5, 1) \
\
START_CYCLE(6) \
set_byte_spc(_address, _PC); \
_SP--; \
_address = 0x0100 + _SP; \
END_CYCLE(6, 1) \
\
START_CYCLE(7) \
/* should we write PSW to stack here? */ \
END_CYCLE(7, 1) \
\
START_CYCLE(8) \
_PC = _address2; \
END_OPCODE(1)
#define COND_REL(TEST) \
/* 2 cycles - opcode, branch logic + offset; */ \
/* +2 cycles (taken branch) add PC to offset, reload PC */ \
\
START_CYCLE(2) \
_offset = get_byte_spc(_PC); \
_PC++; \
END_BRANCH_OPCODE(2, TEST)
#define DP_REL_TEST_BBS \
if (!(_data & offset_to_bit[_opcode >> 5])) \
EXIT_OPCODE(1)
#define DP_REL_TEST_BBC \
if ((_data & offset_to_bit[_opcode >> 5])) \
EXIT_OPCODE(1)
#define TEST_CBNE \
if (_data == _A) \
EXIT_OPCODE(1)
#define DP_REL_TEST_DBNZ \
--_data; \
set_byte_spc(_address, _data); \
if (!_data) \
EXIT_OPCODE(1)
#define COND_DP_REL(TEST) \
/* 5 cycles - opcode, address, branch offset, data read, branch logic */ \
/* and data write (DBNZ only); +2 cycles (taken branch) add PC to */ \
/* offset, reload PC */ \
START_CYCLE(2) \
_address = _dp + get_byte_spc(_PC); \
_PC++; \
END_CYCLE(2, 1) \
\
START_CYCLE(3) \
_offset = get_byte_spc(_PC); \
_PC++; \
END_CYCLE(3, 1) \
\
START_CYCLE(4) \
_data = get_byte_spc(_address); \
END_CYCLE(4, 1) \
\
START_CYCLE(5) \
END_BRANCH_OPCODE(5, TEST)
#define OP_READ_DP(OP, dest) \
/* 3 cycles - opcode, address, data read + op */ \
START_CYCLE(2) \
_address = _dp + get_byte_spc(_PC); \
_PC++; \
END_CYCLE(2, 1) \
\
START_CYCLE(3) \
_data = get_byte_spc(_address); \
OP_##OP((dest), _data) END_OPCODE(1)
/* xxx00100 */
#define OP_READ_DP_A(OP) OP_READ_DP(OP, _A)
#define OP_READ_ABS(OP, dest) \
/* 4 cycles - opcode, address low, address high, data read + op */ \
START_CYCLE(2) \
_address = get_byte_spc(_PC); \
_PC++; \
END_CYCLE(2, 1) \
\
START_CYCLE(3) \
_address += get_byte_spc(_PC) << 8; \
_PC++; \
END_CYCLE(3, 1) \
\
START_CYCLE(4) \
_data = get_byte_spc(_address); \
OP_##OP((dest), _data) END_OPCODE(1)
/* xxx00101 */
#define OP_READ_ABS_A(OP) OP_READ_ABS(OP, _A)
#define OP_READ_INDIRECT(OP, dest) \
/* 3 cycles - opcode, address calc, data read + op */ \
START_CYCLE(2) \
_address = _dp + _X; \
END_CYCLE(2, 1) \
\
START_CYCLE(3) \
_data = get_byte_spc(_address); \
OP_##OP(_A, _data) END_OPCODE(1)
#define OP_RMW_INDIRECT(OP, NEED_OLD_DATA) \
/* 4 cycles - opcode, address calc, data read, data write */ \
START_CYCLE(2) \
_address = _dp + _X; \
END_CYCLE(2, 1) \
\
START_CYCLE(3) \