From a9d5549e14480167ede1b4ddc1e11326e3ffb73c Mon Sep 17 00:00:00 2001
From: stnolting <stnolting@gmail.com>
Date: Tue, 7 Jan 2025 21:23:20 +0100
Subject: [PATCH] [sim] minor testbench edits

---
 sim/neorv32_tb.vhd | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/sim/neorv32_tb.vhd b/sim/neorv32_tb.vhd
index 124a37d3b..003847849 100644
--- a/sim/neorv32_tb.vhd
+++ b/sim/neorv32_tb.vhd
@@ -91,6 +91,13 @@ architecture neorv32_tb_rtl of neorv32_tb is
   signal msi, mei, mti : std_ulogic;
 
   -- slink --
+  type slink_t is record
+    data  : std_ulogic_vector(31 downto 0); -- data
+    addr  : std_ulogic_vector(3 downto 0); -- source/destination ID
+    valid : std_ulogic; -- source valid
+    last  : std_ulogic; -- last element of packet
+    ready : std_ulogic; -- sink ready
+  end record;
   signal slink_tx, slink_rx : slink_t;
 
   -- XBUS (Wishbone b4) bus --