From a9a8e20ca38059b7d0a091d1070c9f286d7db9c2 Mon Sep 17 00:00:00 2001 From: stnolting Date: Mon, 16 Sep 2024 16:59:06 +0200 Subject: [PATCH] =?UTF-8?q?=F0=9F=9A=80=20preparing=20release=20v1.10.4?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- CHANGELOG.md | 1 + docs/attrs.adoc | 2 +- rtl/core/neorv32_package.vhd | 2 +- sw/svd/neorv32.svd | 2 +- 4 files changed, 4 insertions(+), 3 deletions(-) diff --git a/CHANGELOG.md b/CHANGELOG.md index 8b5793274..69caba676 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12 | Date | Version | Comment | Ticket | |:----:|:-------:|:--------|:------:| +| 16.09.2024 | [**:rocket:1.10.4**](https://github.com/stnolting/neorv32/releases/tag/v1.10.4) | **New release** | | | 15.09.2024 | 1.10.3.10 | :bug: SW: fix stack-alignment (has to be 128-bit-aligned) before entering the very first procedure (`main`) | [#1021](https://github.com/stnolting/neorv32/pull/1021) | | 14.09.2024 | 1.10.3.9 | massive rtl code cleanup | [#1019](https://github.com/stnolting/neorv32/pull/1019) | | 14.09.2024 | 1.10.3.8 | :bug: fix `b.ctz` instruction decoding (bug introduced in v1.10.3.6) | [#1018](https://github.com/stnolting/neorv32/pull/1018) | diff --git a/docs/attrs.adoc b/docs/attrs.adoc index ec1fa5c6e..c8357663e 100644 --- a/docs/attrs.adoc +++ b/docs/attrs.adoc @@ -1,6 +1,6 @@ :keywords: neorv32, risc-v, riscv, rv32, fpga, soft-core, vhdl, microcontroller, cpu, soc, processor, gcc, openocd, gdb, verilog, rtl, asip, asic, safety :description: A size-optimized, customizable and highly extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL. -:revnumber: v1.10.3 +:revnumber: v1.10.4 :doctype: book :sectnums: :stem: diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index 2c91d2633..e86ecd7e6 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -29,7 +29,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100310"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100400"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width diff --git a/sw/svd/neorv32.svd b/sw/svd/neorv32.svd index 2cc729cd8..da346f31c 100644 --- a/sw/svd/neorv32.svd +++ b/sw/svd/neorv32.svd @@ -4,7 +4,7 @@ stnolting neorv32 RISC-V - 1.10.3 + 1.10.4 The NEORV32 RISC-V Processor