From 3ae1e28782ed8e3c281a5864434fa1efa51310d6 Mon Sep 17 00:00:00 2001 From: stnolting Date: Sun, 29 Dec 2024 17:26:16 +0100 Subject: [PATCH 1/9] =?UTF-8?q?=E2=9A=A0=EF=B8=8F=20[sysinfo]=20rename=20M?= =?UTF-8?q?EM=20->=20MISC?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit --- docs/datasheet/soc_sysinfo.adoc | 26 +++++++++++++++----------- sw/lib/include/neorv32_sysinfo.h | 18 +++++++++--------- sw/lib/source/neorv32_rte.c | 6 +++--- sw/svd/neorv32.svd | 10 +++++----- 4 files changed, 32 insertions(+), 28 deletions(-) diff --git a/docs/datasheet/soc_sysinfo.adoc b/docs/datasheet/soc_sysinfo.adoc index 575183db8..83b181932 100644 --- a/docs/datasheet/soc_sysinfo.adoc +++ b/docs/datasheet/soc_sysinfo.adoc @@ -42,14 +42,14 @@ to take into account a dynamic frequency scaling of the processor. [options="header",grid="all"] |======================= | Address | Name [C] | R/W | Description -| `0xfffe0000` | `CLK` | r/w | clock frequency in Hz (initialized from top's `CLOCK_FREQUENCY` generic) -| `0xfffe0004` | `MEM[4]` | r/- | internal memory configuration (see <<_sysinfo_memory_configuration>>) -| `0xfffe0008` | `SOC` | r/- | specific SoC configuration (see <<_sysinfo_soc_configuration>>) -| `0xfffe000c` | `CACHE` | r/- | cache configuration information (see <<_sysinfo_cache_configuration>>) +| `0xfffe0000` | `CLK` | r/w | clock frequency in Hz (initialized from top's `CLOCK_FREQUENCY` generic) +| `0xfffe0004` | `MISC[4]` | r/- | miscellaneous system configurations (see <<_sysinfo_miscellaneous_configuration>>) +| `0xfffe0008` | `SOC` | r/- | specific SoC configuration (see <<_sysinfo_soc_configuration>>) +| `0xfffe000c` | `CACHE` | r/- | cache configuration information (see <<_sysinfo_cache_configuration>>) |======================= -===== SYSINFO - Memory Configuration +===== SYSINFO - Miscellaneous Configuration [NOTE] Bit fields in this register are set to all-zero if the according memory system is not implemented. @@ -59,10 +59,10 @@ Bit fields in this register are set to all-zero if the according memory system i [options="header",grid="all"] |======================= | Byte | Name [C] | Description -| `0` | `SYSINFO_MEM_IMEM` | _log2_(internal IMEM size in bytes), via top's `MEM_INT_IMEM_SIZE` generic -| `1` | `SYSINFO_MEM_DMEM` | _log2_(internal DMEM size in bytes), via top's `MEM_INT_DMEM_SIZE` generic -| `2` | - | _reserved_, read as zero -| `3` | `SYSINFO_MEM_BOOT` | boot mode configuration, via top's `BOOT_MODE_SELECT` generic (see <<_boot_configuration>>)) +| `0` | `SYSINFO_MISC_IMEM` | _log2_(internal IMEM size in bytes), via top's `MEM_INT_IMEM_SIZE` generic +| `1` | `SYSINFO_MISC_DMEM` | _log2_(internal DMEM size in bytes), via top's `MEM_INT_DMEM_SIZE` generic +| `2` | `SYSINFO_MISC_HART` | number of physical CPU cores ("harts") +| `3` | `SYSINFO_MISC_BOOT` | boot mode configuration, via top's `BOOT_MODE_SELECT` generic (see <<_boot_configuration>>)) |======================= @@ -110,8 +110,12 @@ Bit fields in this register are set to all-zero if the according memory system i ===== SYSINFO - Cache Configuration -[NOTE] -Bit fields in this register are set to all-zero if the according cache is not implemented. +The SYSINFO cache register provides information about the configuration of the processor caches: + +* <<_processor_internal_instruction_cache_icache>> +* <<_processor_internal_data_cache_dcache>> +* <<_execute_in_place_module_xip>> cache (XIP-CACHE) +* <<_processor_external_bus_interface_xbus>> cache (XBUS-CACHE) .SYSINFO `CACHE` Bits [cols="^1,<10,<10"] diff --git a/sw/lib/include/neorv32_sysinfo.h b/sw/lib/include/neorv32_sysinfo.h index 58d775b34..42922241b 100644 --- a/sw/lib/include/neorv32_sysinfo.h +++ b/sw/lib/include/neorv32_sysinfo.h @@ -25,21 +25,21 @@ /**@{*/ /** SYSINFO module prototype */ typedef volatile struct __attribute__((packed,aligned(4))) { - uint32_t CLK; /**< offset 0: Clock speed in Hz */ - const uint8_t MEM[4]; /**< offset 4: Internal memory sizes (#NEORV32_SYSINFO_MEM_enum) */ - const uint32_t SOC; /**< offset 8: SoC features (#NEORV32_SYSINFO_SOC_enum) */ - const uint32_t CACHE; /**< offset 12: Cache configuration (#NEORV32_SYSINFO_CACHE_enum) */ + uint32_t CLK; /**< offset 0: Clock speed in Hz */ + const uint8_t MISC[4]; /**< offset 4: Miscellaneous system configurations (#NEORV32_SYSINFO_MISC_enum) */ + const uint32_t SOC; /**< offset 8: SoC features (#NEORV32_SYSINFO_SOC_enum) */ + const uint32_t CACHE; /**< offset 12: Cache configuration (#NEORV32_SYSINFO_CACHE_enum) */ } neorv32_sysinfo_t; /** SYSINFO module hardware access (#neorv32_sysinfo_t) */ #define NEORV32_SYSINFO ((neorv32_sysinfo_t*) (NEORV32_SYSINFO_BASE)) -/** NEORV32_SYSINFO.MEM (r/-): Memory configuration (sizes) */ +/** NEORV32_SYSINFO_MISC_enum.MEM (r/-): Miscellaneous system configurations */ enum NEORV32_SYSINFO_MEM_enum { - SYSINFO_MEM_IMEM = 0, /**< SYSINFO_MEM byte 0 (r/-): log2(internal IMEM size in bytes) (via MEM_INT_IMEM_SIZE generic) */ - SYSINFO_MEM_DMEM = 1, /**< SYSINFO_MEM byte 1 (r/-): log2(internal DMEM size in bytes) (via MEM_INT_DMEM_SIZE generic) */ - SYSINFO_MEM_res = 2, /**< SYSINFO_MEM byte 2 (r/-): reserved, read as zero */ - SYSINFO_MEM_BOOT = 3 /**< SYSINFO_MEM byte 3 (r/-): boot mode configuration (via BOOT_MODE_SELECT generic) */ + SYSINFO_MISC_IMEM = 0, /**< SYSINFO_MISC byte 0 (r/-): log2(internal IMEM size in bytes) (via MEM_INT_IMEM_SIZE generic) */ + SYSINFO_MISC_DMEM = 1, /**< SYSINFO_MISC byte 1 (r/-): log2(internal DMEM size in bytes) (via MEM_INT_DMEM_SIZE generic) */ + SYSINFO_MISC_HART = 2, /**< SYSINFO_MISC byte 2 (r/-): number of physical CPU cores ("harts") */ + SYSINFO_MISC_BOOT = 3 /**< SYSINFO_MISC byte 3 (r/-): boot mode configuration (via BOOT_MODE_SELECT generic) */ }; /** NEORV32_SYSINFO.SOC (r/-): Implemented processor devices/features */ diff --git a/sw/lib/source/neorv32_rte.c b/sw/lib/source/neorv32_rte.c index 5698f4eae..408e8b481 100644 --- a/sw/lib/source/neorv32_rte.c +++ b/sw/lib/source/neorv32_rte.c @@ -527,7 +527,7 @@ void neorv32_rte_print_hw_config(void) { } neorv32_uart0_printf("\nBoot configuration: "); - int boot_config = (int)(NEORV32_SYSINFO->MEM[SYSINFO_MEM_BOOT]); + int boot_config = (int)(NEORV32_SYSINFO->MISC[SYSINFO_MISC_BOOT]); switch (boot_config) { case 0: neorv32_uart0_printf("boot via bootloader (0)\n"); break; case 1: neorv32_uart0_printf("boot from custom address (1)\n"); break; @@ -538,7 +538,7 @@ void neorv32_rte_print_hw_config(void) { // internal IMEM neorv32_uart0_printf("Internal IMEM: "); if (NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_MEM_INT_IMEM)) { - neorv32_uart0_printf("%u bytes\n", (uint32_t)(1 << NEORV32_SYSINFO->MEM[SYSINFO_MEM_IMEM]) & 0xFFFFFFFCUL); + neorv32_uart0_printf("%u bytes\n", (uint32_t)(1 << NEORV32_SYSINFO->MISC[SYSINFO_MISC_IMEM]) & 0xFFFFFFFCUL); } else { neorv32_uart0_printf("none\n"); @@ -547,7 +547,7 @@ void neorv32_rte_print_hw_config(void) { // internal DMEM neorv32_uart0_printf("Internal DMEM: "); if (NEORV32_SYSINFO->SOC & (1 << SYSINFO_SOC_MEM_INT_DMEM)) { - neorv32_uart0_printf("%u bytes\n", (uint32_t)(1 << NEORV32_SYSINFO->MEM[SYSINFO_MEM_DMEM]) & 0xFFFFFFFCUL); + neorv32_uart0_printf("%u bytes\n", (uint32_t)(1 << NEORV32_SYSINFO->MISC[SYSINFO_MISC_DMEM]) & 0xFFFFFFFCUL); } else { neorv32_uart0_printf("none\n"); diff --git a/sw/svd/neorv32.svd b/sw/svd/neorv32.svd index 9172ba4d5..356a415c1 100644 --- a/sw/svd/neorv32.svd +++ b/sw/svd/neorv32.svd @@ -1745,14 +1745,14 @@ MEM - Memory configuration (sizes) + Miscellaneous system configurations 0x04 read-only - SYSINFO_MEM_IMEM[7:0]log2(IMEM size in bytes) - SYSINFO_MEM_DMEM[15:8]log2(DMEM size in bytes) - SYSINFO_MEM_res[23:16]yet unused - SYSINFO_MEM_BOOT[31:24]Boot mode configuration select + SYSINFO_MISC_IMEM[7:0]log2(IMEM size in bytes) + SYSINFO_MISC_DMEM[15:8]log2(DMEM size in bytes) + SYSINFO_MISC_HART[23:16]Number of physical CPU cores + SYSINFO_MISC_BOOT[31:24]Boot mode configuration select From 90814e2213a0754c2d2365ce5ba80158c3faf52b Mon Sep 17 00:00:00 2001 From: stnolting Date: Sun, 29 Dec 2024 17:26:43 +0100 Subject: [PATCH 2/9] [sysinfo] add number of harts to MISC --- rtl/core/neorv32_sysinfo.vhd | 3 ++- rtl/core/neorv32_top.vhd | 1 + sw/lib/source/neorv32_rte.c | 2 ++ 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/rtl/core/neorv32_sysinfo.vhd b/rtl/core/neorv32_sysinfo.vhd index 65f5003b0..168eea9d6 100644 --- a/rtl/core/neorv32_sysinfo.vhd +++ b/rtl/core/neorv32_sysinfo.vhd @@ -17,6 +17,7 @@ use neorv32.neorv32_package.all; entity neorv32_sysinfo is generic ( + NUM_HARTS : natural; -- number of physical CPU cores CLOCK_FREQUENCY : natural; -- clock frequency of clk_i in Hz BOOT_MODE_SELECT : natural; -- boot configuration select (default = 0 = bootloader) INT_BOOTLOADER_EN : boolean; -- boot configuration: true = boot explicit bootloader; false = boot from int/ext (I)MEM @@ -106,7 +107,7 @@ begin -- SYSINFO(1): Misc -- sysinfo(1)(7 downto 0) <= std_ulogic_vector(to_unsigned(index_size_f(MEM_INT_IMEM_SIZE), 8)); -- log2(IMEM size) sysinfo(1)(15 downto 8) <= std_ulogic_vector(to_unsigned(index_size_f(MEM_INT_DMEM_SIZE), 8)); -- log2(DMEM size) - sysinfo(1)(23 downto 16) <= (others => '0'); -- reserved + sysinfo(1)(23 downto 16) <= std_ulogic_vector(to_unsigned(NUM_HARTS, 8)); -- number of physical CPU cores sysinfo(1)(31 downto 24) <= std_ulogic_vector(to_unsigned(BOOT_MODE_SELECT, 8)); -- boot configuration -- SYSINFO(2): SoC Configuration -- diff --git a/rtl/core/neorv32_top.vhd b/rtl/core/neorv32_top.vhd index f26ed825a..a7857e8b5 100644 --- a/rtl/core/neorv32_top.vhd +++ b/rtl/core/neorv32_top.vhd @@ -1592,6 +1592,7 @@ begin if io_sysinfo_en_c generate neorv32_sysinfo_inst: entity neorv32.neorv32_sysinfo generic map ( + NUM_HARTS => 1, CLOCK_FREQUENCY => CLOCK_FREQUENCY, BOOT_MODE_SELECT => BOOT_MODE_SELECT, INT_BOOTLOADER_EN => bootrom_en_c, diff --git a/sw/lib/source/neorv32_rte.c b/sw/lib/source/neorv32_rte.c index 408e8b481..1cb1fffb2 100644 --- a/sw/lib/source/neorv32_rte.c +++ b/sw/lib/source/neorv32_rte.c @@ -399,6 +399,8 @@ void neorv32_rte_print_hw_config(void) { if (neorv32_cpu_csr_read(CSR_MXISA) & (1 << CSR_MXISA_IS_SIM)) { neorv32_uart0_printf("yes\n"); } else { neorv32_uart0_printf("no\n"); } + neorv32_uart0_printf("CPU cores (harts): %u\n", (uint32_t)NEORV32_SYSINFO->MISC[SYSINFO_MISC_HART]); + neorv32_uart0_printf("Clock speed: %u Hz\n", neorv32_sysinfo_get_clk()); neorv32_uart0_printf("Clock gating: "); From f8b06121bd23d4c5f0e1e7a7765720a43ef3b7db Mon Sep 17 00:00:00 2001 From: stnolting Date: Sun, 29 Dec 2024 17:26:53 +0100 Subject: [PATCH 3/9] [package] update version ID --- rtl/core/neorv32_package.vhd | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/core/neorv32_package.vhd b/rtl/core/neorv32_package.vhd index a2210e98d..fbff06bfe 100644 --- a/rtl/core/neorv32_package.vhd +++ b/rtl/core/neorv32_package.vhd @@ -29,7 +29,7 @@ package neorv32_package is -- Architecture Constants ----------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- - constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100803"; -- hardware version + constant hw_version_c : std_ulogic_vector(31 downto 0) := x"01100804"; -- hardware version constant archid_c : natural := 19; -- official RISC-V architecture ID constant XLEN : natural := 32; -- native data path width From 78854f2661f7090ac202ec362b417e91f52e8c35 Mon Sep 17 00:00:00 2001 From: stnolting Date: Sun, 29 Dec 2024 17:27:24 +0100 Subject: [PATCH 4/9] [rtl] minor cleanups --- rtl/core/neorv32_bus.vhd | 5 +---- rtl/core/neorv32_debug_auth.vhd | 12 ++++++------ rtl/core/neorv32_debug_dtm.vhd | 4 ++-- 3 files changed, 9 insertions(+), 12 deletions(-) diff --git a/rtl/core/neorv32_bus.vhd b/rtl/core/neorv32_bus.vhd index bf03d9224..df37c77d5 100644 --- a/rtl/core/neorv32_bus.vhd +++ b/rtl/core/neorv32_bus.vhd @@ -1,8 +1,5 @@ -- ================================================================================ -- --- NEORV32 SoC - Processor Bus Infrastructure: Prioritizing 2-to-1 Bus Switch -- --- -------------------------------------------------------------------------------- -- --- Allows to access a single device bus X by two controller ports A and B. -- --- Controller port A has priority over controller port B. -- +-- NEORV32 SoC - Processor Bus Infrastructure: 2-to-1 Bus Switch -- -- -------------------------------------------------------------------------------- -- -- The NEORV32 RISC-V Processor - https://github.com/stnolting/neorv32 -- -- Copyright (c) NEORV32 contributors. -- diff --git a/rtl/core/neorv32_debug_auth.vhd b/rtl/core/neorv32_debug_auth.vhd index c264cf98e..efe5b0b3b 100644 --- a/rtl/core/neorv32_debug_auth.vhd +++ b/rtl/core/neorv32_debug_auth.vhd @@ -1,5 +1,5 @@ -- ================================================================================ -- --- NEORV32 SoC - RISC-V-Compatible Authentication Module for the On-Chip Debugger -- +-- NEORV32 OCD - RISC-V-Compatible Authentication Module for the On-Chip Debugger -- -- -------------------------------------------------------------------------------- -- -- Note that this module (in its default state) just provides a very simple and -- -- UNSECURE authentication mechanism that is meant as an example to showcase the -- @@ -39,7 +39,7 @@ end neorv32_debug_auth; architecture neorv32_debug_auth_rtl of neorv32_debug_auth is - signal authenticated : std_ulogic; + signal authenticated_q : std_ulogic; begin @@ -53,12 +53,12 @@ begin dm_controller: process(rstn_i, clk_i) begin if (rstn_i = '0') then - authenticated <= '0'; + authenticated_q <= '0'; elsif rising_edge(clk_i) then if (enable_i = '0') then - authenticated <= '0'; -- clear authentication when disabled + authenticated_q <= '0'; -- clear authentication when disabled elsif (we_i = '1') then - authenticated <= wdata_i(0); -- just write a 1 to authenticate + authenticated_q <= wdata_i(0); -- just write a "1" to authenticate end if; end if; end process dm_controller; @@ -67,7 +67,7 @@ begin busy_o <= '0'; -- this simple authenticator is always ready -- authentication passed -- - valid_o <= authenticated; + valid_o <= authenticated_q; -- read data -- rdata_o <= (others => '0'); -- there is nothing to read here diff --git a/rtl/core/neorv32_debug_dtm.vhd b/rtl/core/neorv32_debug_dtm.vhd index 8b97e53b0..901025afe 100644 --- a/rtl/core/neorv32_debug_dtm.vhd +++ b/rtl/core/neorv32_debug_dtm.vhd @@ -1,5 +1,5 @@ -- ================================================================================ -- --- NEORV32 SoC - RISC-V-Compatible Debug Transport Module (DTM) -- +-- NEORV32 OCD - RISC-V-Compatible Debug Transport Module (DTM) -- -- -------------------------------------------------------------------------------- -- -- Compatible to RISC-V debug spec. versions 0.13 and 1.0. -- -- -------------------------------------------------------------------------------- -- @@ -111,7 +111,7 @@ begin tap_sync.tdi <= tap_sync.tdi_ff(2); - -- Tap Control FSM ------------------------------------------------------------------------ + -- JTAG Tap Control FSM ------------------------------------------------------------------- -- ------------------------------------------------------------------------------------------- tap_control: process(rstn_i, clk_i) begin From 2a5470bb910bf6c787370117024233479ebdbe78 Mon Sep 17 00:00:00 2001 From: stnolting Date: Sun, 29 Dec 2024 17:27:32 +0100 Subject: [PATCH 5/9] [docs] typo fix --- docs/datasheet/soc_xbus.adoc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/datasheet/soc_xbus.adoc b/docs/datasheet/soc_xbus.adoc index 837999d42..64760fb1c 100644 --- a/docs/datasheet/soc_xbus.adoc +++ b/docs/datasheet/soc_xbus.adoc @@ -110,7 +110,7 @@ It compatible to the the AXI4 `ARPROT` and `AWPROT` signals. * `xbus_tag_o(2)` **I**: access is an **instruction** fetch when set; access is a data access when cleared -**External Bus Cache (X-CACHE)** +**External Bus Cache (XBUS-CACHE)** The XBUS interface provides an optional internal cache that can be used to buffer processor-external accesses. The x-cache is enabled via the `XBUS_CACHE_EN` generic. The total size of the cache is split into the number of From 68d5c13ec47d0066b83046127c2644033aca7c8c Mon Sep 17 00:00:00 2001 From: stnolting Date: Sun, 29 Dec 2024 17:34:28 +0100 Subject: [PATCH 6/9] [pmp] tie unused signals to zero --- rtl/core/neorv32_cpu_pmp.vhd | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/rtl/core/neorv32_cpu_pmp.vhd b/rtl/core/neorv32_cpu_pmp.vhd index daf22ce85..5f2dc6fcc 100644 --- a/rtl/core/neorv32_cpu_pmp.vhd +++ b/rtl/core/neorv32_cpu_pmp.vhd @@ -251,10 +251,9 @@ begin region_gen: for r in 0 to NUM_REGIONS-1 generate - -- naturally-aligned address mask -- + -- NAPOT address mask -- nap_mode_enable: if NAP_EN generate - -- compute address masks for NAPOT mode -- addr_mask_napot(r)(pmp_lsb_c) <= '0'; addr_mask_napot_gen: @@ -275,9 +274,15 @@ begin end if; end if; end process addr_masking; - end generate; -- /nap_mode_enable + -- NAPOT disabled -- + nap_mode_disable: + if not NAP_EN generate + addr_mask_napot <= (others => (others => '0')); + addr_mask <= (others => (others => '0')); + end generate; + -- check region address match -- -- NA4 and NAPOT -- From f331251f180294831fda0b80368e68013edba3a2 Mon Sep 17 00:00:00 2001 From: stnolting Date: Sun, 29 Dec 2024 17:38:56 +0100 Subject: [PATCH 7/9] [changelog] add v1.10.8.4 --- CHANGELOG.md | 1 + 1 file changed, 1 insertion(+) diff --git a/CHANGELOG.md b/CHANGELOG.md index 1198cd9d6..d6c883b86 100644 --- a/CHANGELOG.md +++ b/CHANGELOG.md @@ -29,6 +29,7 @@ mimpid = 0x01040312 -> Version 01.04.03.12 -> v1.4.3.12 | Date | Version | Comment | Ticket | |:----:|:-------:|:--------|:------:| +| 29.12.2024 | 1.10.8.4 | :warning: rename `SYSINFO.MEM -> SYSINFO.MISC`; add new `SYSINFO-MISC` entry for number of CPU cores (hardwired to one) | [#1134](https://github.com/stnolting/neorv32/pull/1134) | | 29.12.2024 | 1.10.8.3 | :bug: fix incorrect HPM counter sizes if `HPM_CNT_WIDTH = 64` | [#1128](https://github.com/stnolting/neorv32/pull/1128) | | 27.12.2024 | 1.10.8.2 | add out-of-band signals to internal request bus | [#1131](https://github.com/stnolting/neorv32/pull/1131) | | 27.12.2024 | 1.10.8.1 | :warning: replace MTIME by CLINT; :warning: remove `HART_ID` generic | [#1130](https://github.com/stnolting/neorv32/pull/1130) | From d79b605dee8c9f416593b0faf7eedb7154c0273b Mon Sep 17 00:00:00 2001 From: stnolting Date: Sun, 29 Dec 2024 17:39:20 +0100 Subject: [PATCH 8/9] [bootloader] update for SYSINFO.MISC --- sw/bootloader/bootloader.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sw/bootloader/bootloader.c b/sw/bootloader/bootloader.c index fdc1da2f9..ce411d9ea 100644 --- a/sw/bootloader/bootloader.c +++ b/sw/bootloader/bootloader.c @@ -305,9 +305,9 @@ int main(void) { PRINT_TEXT("\nSOC: "); PRINT_XNUM(NEORV32_SYSINFO->SOC); PRINT_TEXT("\nIMEM: "); - PRINT_XNUM((uint32_t)(1 << NEORV32_SYSINFO->MEM[SYSINFO_MEM_IMEM]) & 0xFFFFFFFCUL); + PRINT_XNUM((uint32_t)(1 << NEORV32_SYSINFO->MISC[SYSINFO_MISC_IMEM]) & 0xFFFFFFFCUL); PRINT_TEXT("\nDMEM: "); - PRINT_XNUM((uint32_t)(1 << NEORV32_SYSINFO->MEM[SYSINFO_MEM_DMEM]) & 0xFFFFFFFCUL); + PRINT_XNUM((uint32_t)(1 << NEORV32_SYSINFO->MISC[SYSINFO_MISC_DMEM]) & 0xFFFFFFFCUL); PRINT_TEXT("\n"); From f668861a269a937cf6ebdf443518a172c4f0e579 Mon Sep 17 00:00:00 2001 From: stnolting Date: Sun, 29 Dec 2024 19:05:56 +0100 Subject: [PATCH 9/9] [sw/lib] typo fixes --- sw/lib/include/neorv32_sysinfo.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/sw/lib/include/neorv32_sysinfo.h b/sw/lib/include/neorv32_sysinfo.h index 42922241b..e15b9a580 100644 --- a/sw/lib/include/neorv32_sysinfo.h +++ b/sw/lib/include/neorv32_sysinfo.h @@ -34,8 +34,8 @@ typedef volatile struct __attribute__((packed,aligned(4))) { /** SYSINFO module hardware access (#neorv32_sysinfo_t) */ #define NEORV32_SYSINFO ((neorv32_sysinfo_t*) (NEORV32_SYSINFO_BASE)) -/** NEORV32_SYSINFO_MISC_enum.MEM (r/-): Miscellaneous system configurations */ -enum NEORV32_SYSINFO_MEM_enum { +/** NEORV32_SYSINFO.MISC (r/-): Miscellaneous system configurations */ +enum NEORV32_SYSINFO_MISC_enum { SYSINFO_MISC_IMEM = 0, /**< SYSINFO_MISC byte 0 (r/-): log2(internal IMEM size in bytes) (via MEM_INT_IMEM_SIZE generic) */ SYSINFO_MISC_DMEM = 1, /**< SYSINFO_MISC byte 1 (r/-): log2(internal DMEM size in bytes) (via MEM_INT_DMEM_SIZE generic) */ SYSINFO_MISC_HART = 2, /**< SYSINFO_MISC byte 2 (r/-): number of physical CPU cores ("harts") */