diff --git a/docs/datasheet/on_chip_debugger.adoc b/docs/datasheet/on_chip_debugger.adoc
index 0ec7c5ed4..49b8c1e40 100644
--- a/docs/datasheet/on_chip_debugger.adoc
+++ b/docs/datasheet/on_chip_debugger.adoc
@@ -510,34 +510,43 @@ and the debugger-controlled DM. This register is used to communicate requests, w
 DM, and the according acknowledges, which are generated by the CPU. The status register is sub-divided into four
 consecutive memory-mapped registers.
 
-The functionality of the first register (offset 0) depends on whether the CPU accesses the register in read or write
-mode. In read mode, the register provides the resume and execute requests for four individual harts. The according
-flags are placed in individual byes so the CPU can use load-byte instructions with the hart ID as byte-offset to load
-the hart-specific request flags.
-
-All four status register provide a write mode. Writing the hart ID to the first register (offset 0) acknowledges the
-**HALT** request for that specific hart. Writing the hart ID to the second register (offset 4) acknowledges the
-**RESUME** request for that specific hart. Writing the hart ID to the third register (offset 8) acknowledges the
-**EXECUTE** request for that specific hart. Writing any data to the fourth register (offset 12) acknowledged an
-**EXCEPTION** encountered during execution of the program buffer.
-
-.DM Status Register - CPU Access
-[cols="^1,^1,^1,<10"]
+Starting at `0xffffff80` the status register provides a set of memory-mapped interface register whose functionality
+depends on whether the CPU accesses the register in read or write mode. **Read** accesses return the **requests**
+for each individual hart generated by the DM. **Write** accesses are used to **acknowledge** these requests by the
+individual harts back to the DM.
+
+For read accesses, the hart ID is used as byte offset to read the hart-specific request flags. The flags for hart 0
+are located at `0xffffff80 + 0`, the flags for hart 1 are located at `0xffffff80 + 1` and so on. Hence, each hart
+can use load-unsigned-byte instructions to isolate the hart specific flags.
+
+.DM Status Register - Read Access (byte-wise access)
+[cols="^2,^1,^1,^1,<6"]
+[options="header",grid="rows"]
+|=======================
+| Address            | Hart | R/W  | Bits | Description
+.2+| `0xffffff80` .2+| 0 .2+| r/- ^| 0   <| Resume request
+                                  ^| 1   <| Execute request
+.2+| `0xffffff81` .2+| 1 .2+| r/- ^| 0   <| Resume request
+                                  ^| 1   <| Execute request
+.2+| `0xffffff82` .2+| 2 .2+| r/- ^| 0   <| Resume request
+                                  ^| 1   <| Execute request
+.2+| `0xffffff83` .2+| 3 .2+| r/- ^| 0   <| Resume request
+                                  ^| 1   <| Execute request
+|=======================
+
+For write accesses, four consecutive memory-mapped registers are implemented. Each individual register is used
+to acknowledge a specific condition: halt, resume, execute and exception. Each hart can acknowledge the according
+condition by writing its hart ID to the according register.
+
+.DM Status Register - Write Access (word-wise access)
+[cols="^2,^1,^1,<6"]
 [options="header",grid="rows"]
 |=======================
-| Offset  | R/W | Bits  | Description
-.9+| 0 .8+| r/- |     0 <| Hart 0: RESUME request
-                |     1 <| Hart 0: EXECUTE request
-                |     8 <| Hart 1: RESUME request
-                |     9 <| Hart 1: EXECUTE request
-                |    16 <| Hart 2: RESUME request
-                |    17 <| Hart 2: EXECUTE request
-                |    24 <| Hart 3: RESUME request
-                |    25 <| Hart 3: EXECUTE request
-          | -/w |   1:0 <| Write hart ID (0..3) to acknowledge HALT
-|       4 | -/w |   1:0 <| Write hart ID (0..3) to acknowledge RESUME
-|       8 | -/w |   1:0 <| Write hart ID (0..3) to acknowledge EXECUTE
-|      12 | -/w |     - <| Write any value to acknowledge EXCEPTION
+| Address      | R/W | Bits | Description
+| `0xffffff80` | r/w | 1:0  | write hart ID to send hart's HALT acknowledge
+| `0xffffff84` | r/w | 1:0  | write hart ID to send hart's RESUME acknowledge
+| `0xffffff88` | r/w | 1:0  | write hart ID to send hart's EXECUTE acknowledge
+| `0xffffff8c` | r/w | 1:0  | write any value to send hart's EXCEPTION acknowledge
 |=======================