Not that suitable question about register

[schrodinger1772]

Hi，

I meet some problem with stm32f401 again, maybe that is not that suitable question. But I can not find a palace for the answer. I thought that there must have someone who is master enough for my question or know the palace I can found the answer. Thanks a lot!!!!

here we go. I wanna use the register to config the clock of the core. So I searched for the register for the f401 and give the right cr and pllconfigr. And I have waited for the ready bit of the HSE and PLL. So, I turned to the cfgr, But when i want to write the register like: unsafe{ptr::write_volatile(register_rcc_cfgr as *mut u32, cfgr_sys_value)}; the core will locked. But if I choose the other clock source not pll, It could worked well. So why that thing happened?

I am really really thanks for your time. forgive my ignorance!

the code just show as followed.

loop{
        let mut cr_value =unsafe{ptr::read_volatile(register_rcc_cr).read()};
        let is_25_bit_set = (cr_value & (1 << 25)) != 0;
        let is_17_bit_set = (cr_value & (1 << 17)) != 0;
        if is_25_bit_set && is_17_bit_set{
            break;
        }
    }
    let mut cr_value =unsafe{ptr::read_volatile(register_rcc_cr).read()};
    defmt::println!("afterloop value: {:b}",cr_value);
    let register_rcc_cfgr = unsafe{(RCC_BASE as *mut RW<u32>).offset(0x08 / 4)}; // GPIOC_MODER
    let mut cfgr_sys_value = unsafe{ptr::read_volatile(register_rcc_cfgr).read()};
    // cfgr_value &= !(0b11111 << 16); 
    // cfgr_value |= 0b01000 << 16; // 设置为rtc_pre
    // cfgr_value &= !(0b111 << 13); 
    // cfgr_value |= 0b000 << 13; // 设置为rtc_apb2
    cfgr_sys_value &= !(0b111 << 10);
    cfgr_sys_value |= 0b100 << 10; // 设置为rtc_apb2
    cfgr_sys_value &= !(0b11 << 0); 
    cfgr_sys_value |= 0b10 << 0; // 设置SYS_CLK
    cfgr_sys_value &= !(0b1111 << 4); 
    cfgr_sys_value |= 0b0000 << 4; // 设置SYS_CLK PRE
    unsafe{ptr::write_volatile(register_rcc_cfgr as *mut u32, cfgr_sys_value)};

shevshy

[burrbull]

I don't know answer. Only tried to rewrite in terms of PAC.

let rcc = &(*RCC::ptr());
while {
    let cr = rcc.cr().read();
    !(cr.pllrdy().bit_is_set() && cr.hserdy().bit_is_set())
} { }
let mut cr_value = rcc.cr().read().bits();
defmt::println!("afterloop value: {:b}", cr_value);
rcc.cfgr().modify(|r, w| {
    // w.rtcpre().bits(8);
    // w.ppre2().div1();
    w.ppre1().div2();
    w.sw().pll();
    w.hpre().div1()
}

[schrodinger1772]

Hi, Thanks for your reply! Alought that is a roud question, you still answered that! Thanks a lot!

That is a really interesting writing style. I know I can learn something new from you. Thanks again. by the way, I know why the system will lock this moring, that's because flash haven't wait for several clock.

anyway, Thank you!!!

shevshy