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We were thinking about stability/repeatability of Fastino-DIOT and HVAMP V2 recently so I performed the following estimate for a worst case tempco of the full system:
Adding them all up to get the worst case: 329 uV/°C or 8.2 ppm/°C
Assumptions:
LT3042 reference buffer is in loop with ADA4528 and therefore compensated
Used "tracking" (aka relative between in-package resistors) tempco for all Vishay resistor networks
Is there anything obviously wrong with my estimate? The real devices will likely be a lot better than the worst cases from the datasheets and might even cancel out if we're lucky.
The Vishay resistor network for HVAMP is the only SOIC-16 10K one I found. Is there a better one? That is obviously the biggest contributor to thermal instability on paper.
I cannot think of any hysteresis in the system which would lead to repeatability issues apart from thermal.
We would like to perform our own tests, ideally even with a thermal chamber some time in the future. I'll post the results once we can show them.
The text was updated successfully, but these errors were encountered:
We were thinking about stability/repeatability of Fastino-DIOT and HVAMP V2 recently so I performed the following estimate for a worst case tempco of the full system:
Adding them all up to get the worst case: 329 uV/°C or 8.2 ppm/°C
Assumptions:
Is there anything obviously wrong with my estimate? The real devices will likely be a lot better than the worst cases from the datasheets and might even cancel out if we're lucky.
The Vishay resistor network for HVAMP is the only SOIC-16 10K one I found. Is there a better one? That is obviously the biggest contributor to thermal instability on paper.
I cannot think of any hysteresis in the system which would lead to repeatability issues apart from thermal.
We would like to perform our own tests, ideally even with a thermal chamber some time in the future. I'll post the results once we can show them.
The text was updated successfully, but these errors were encountered: