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Just a quick response to the message[1]. The RVI and ISCAS (Institute of Software Chinese Academy of Sciences)[2] are building the first RISC-V Lab for the RISC-V community. We are going to provide ssh access to almost all RISC-V development boards that we can acquire. The PLCT Lab (part of ISCAS) has managed to get ≥110 Unmatched boards in the last year, and we are ordering an extra one hundred Unmatched boards on the way. We were planning to put ~500 HiFive Unmatched boards in the (first) RISC-V Lab[3].
Although the cancellation of further builds of Unmatched boards may cut the total capacity of Unmatched down to ~200, We're still optimistic that we can serve all the communities which need to run CI on Unmatched. Besides, the RISC-V Lab is also providing hundreds of Nezha D1 boards and QEMU VMs with more than 2k vcores.
Currently the RISC-V Lab is under beta testing and has already served 10+ open source communities. If you are porting open source projects for RISC-V, or want to try CI/CD on RISC-V platform, feel free send a PR with your GitHub ID to [4].
I've been in contact with Wei if there are plans for bare metal access also, and he said this is on the roadmap for 2022, but may happen only later this year. So let's see if we can make this work.
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Recently there has been a posting on one of the RISC-V mailing list about a RISC-V hardware test becoming available (see https://lists.riscv.org/g/software/message/175):
I've been in contact with Wei if there are plans for bare metal access also, and he said this is on the roadmap for 2022, but may happen only later this year. So let's see if we can make this work.
The text was updated successfully, but these errors were encountered: